1. Manuals
  2. Brands
  3. LSI Manuals
  4. Controller
  5. LSI53C1510
  6. Technical manual

LSI LSI53C1510 Technical Manual

I2o-ready pci raid ultra2 scsi controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
TECHNICAL
MANUAL
LSI53C1510
I
O-Ready
2
PCI RAID Ultra2
SCSI Controller
Version 2.2
A p r i l 2 0 0 1
®
S14024.B

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the LSI53C1510 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for LSI LSI53C1510

Summary of Contents for LSI LSI53C1510

  • Page 1 TECHNICAL MANUAL LSI53C1510 O-Ready PCI RAID Ultra2 SCSI Controller Version 2.2 A p r i l 2 0 0 1 ® S14024.B...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Preface This book is the primary reference and technical manual for the LSI Logic Corporation LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller. It contains a complete functional description for the product and includes complete physical and electrical specifications. This technical manual assumes the user is familiar with the current and proposed standards for SCSI and PCI.
  • Page 4 • Chapter 5, Registers (Nonintelligent Mode), describes the PCI and host interface registers that are visible to the host in nonintelligent mode. • Chapter 6, Registers (Intelligent Mode), describes the PCI and host interface registers that are visible to the host in intelligent mode. •...
  • Page 5 LSI Logic World Wide Web Home Page www.lsil.com PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 O (Intelligent Input/Output) SIG Web Site http:\\www.i2osig.org LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller Programming...
  • Page 6 Preliminary. Change bars mark all changes. In Chapter 7, all GPIO0_FETCH/ and GPIO1_MASTER/ items were deleted. 1/00 Final Version. 11/00 Updated Table 7.2 Operating Conditions. All product names changed from SYM to LSI. 4/01 Updated DC electrical specifications and test conditions. Preface...

  • Page 7: Table Of Contents

    Ultra2 SCSI Benefits 1.4.2 LVDlink™ Benefits ® 1.4.3 TolerANT Technology Benefits 1.4.4 I2O Benefits 1.4.5 PAE Benefits 1.4.6 ARM7TDMI RISC Processor Benefits LSI53C1510 Benefits Summary 1.5.1 PCI Performance 1.5.2 SCSI Performance 1.5.3 RAID Performance 1.5.4 Testability 1.5.5 Integration 1-10 1.5.6...
  • Page 8 The Host Interface 2-11 2.2.1 Messages 2-11 2.2.2 Message Transport 2-11 2.2.3 Request Message 2-12 2.2.4 Reply Message 2-14 LSI53C1510 Protocol Engine 2-16 2.3.1 Random Block Storage Class 2-16 Support Components 2-18 2.4.1 DRAM Memory 2-19 2.4.2 Flash ROM 2-19 2.4.3...
  • Page 9 3.3.8 Variable Stripe Size 3.3.9 Online Dynamic Capacity Expansion 3.3.10 Online RAID Level Migration/Reconfiguration 3.3.11 Battery Backup Support and Cache Recovery 3.3.12 Supports SAF-TE SDMS Software Memory Requirements Chapter 4 Signal Descriptions Signal Groupings PCI Interface Signals 4.2.1 System Signals 4.2.2 Address and Data Signals 4.2.3...
  • Page 10 Chapter 5 Registers (Nonintelligent Mode) PCI Functional Description (Nonintelligent Mode) 5.1.1 PCI Addressing 5.1.2 PCI Bus Commands and Functions Supported 5.1.3 Internal Arbiter 5.1.4 PCI Cache Mode PCI Configuration Registers (Nonintelligent Mode) 5-10 Differences from the LSI53C895 and the LSI53C896 5-26 Chapter 6 Registers (Intelligent Mode)
  • Page 11 Figures LSI53C1510 Block Diagram Typical LSI53C1510 Mainboard Applications 1-11 Typical LSI53C1510 Host Adapter Board Application 1-12 LSI53C1510 Block Diagram Example of LSI53C1510 Physical Configurations Hardware Messaging Unit 2-10 LSI53C1510 Request Message Transport 2-14 LSI53C1510 Reply Message Transport 2-15 Typical Implementations...
  • Page 12 7-38 7.27 Target Asynchronous Receive 7-38 7.28 Initiator and Target Synchronous Transfer 7-42 7.29 Left Half of the LSI53C1510 388 BGA Chip - Top View 7-44 7.30 LSI53C1510 388 Ball Grid Array 7-48 7.31 388 PBGA (II) Mechanical Drawing 7-49...
  • Page 13 PCI Configuration Register Map LSI53C1510 Host Interface Register Map 6-19 Absolute Maximum Stress Ratings Operating Conditions LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/,...
  • Page 14 80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 7-42 7.40 Signal Names and BGA Position 7-46 7.41 Signal Names By BGA Position 7-47 LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map LSI53C1510 PCI Registers (Intelligent Mode) Register LSI53C1510 Host Interface Registers (Intelligent Mode) Contents...

  • Page 15: Introduction

    Chapter 1 Introduction This chapter provides a general overview of the LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller. The chapter contains the following sections: • Section 1.1, “General Description,” page 1-1 • Section 1.2, “Module Overviews,” page 1-3 •...

  • Page 16: Block Diagram

    RAID solution. Therefore, this manual describes the hardware and software only in enough detail for system intergrators to design the LSI53C1510 onto a motherboard or a host adapter board. The O RAID software consists of the LSI Logic I O RAID Device Driver Module (DDM), SYMplicity™...

  • Page 17: Module Overviews

    1.2 Module Overviews This section provides an overview of the six major LSI53C1510 modules, which consist of the PCI Interface, Memory Controller, I O Messaging Unit, ARM7TDMI RISC Processor, RAID PAE and SCSI Cores. Chapter 2, “Functional Description,” provides a detailed description of the functions of each module.

  • Page 18: Arm7Tdmi Risc Processor

    In nonintelligent mode, the LSI53C1510 is fully supported by the Storage Device Management System (SDMS™), a software package that supports the Advanced SCSI Protocol Interface (ASPI). SDMS software provides BIOS and driver support for hard disk, tape, removable media products, and CD-ROM under the major PC operating systems.

  • Page 19: Features List

    In intelligent mode, the LSI53C1510 is a complete, single chip RAID solution for the motherboard—just add memory. The RAID product solution consists of a RAID SYMplicity Storage Manager, SYMplicity O RAID firmware with Wind River System IxWorks, and hardware. 1.3.1 Features List •...

  • Page 20: Lvdlink™ Benefits

    40 Mbytes/s, which results in approximately double the synchronous transfer rate of Ultra SCSI. The LSI53C1510 can perform 16-bit (wide), Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing.

  • Page 21: I2O Benefits

    SCSI operations. TolerANT input signal filtering is a built-in feature of the LSI53C1510 and all LSI Logic fast SCSI, Ultra SCSI, and Ultra2 SCSI devices. The benefits of TolerANT technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved Ultra2 SCSI transfer rates.

  • Page 22: Arm7Tdmi Risc Processor Benefits

    I/O from start to finish without host intervention. This frees the host CPU for other processing activity and improves I/O performance. 1.5 LSI53C1510 Benefits Summary This section provides a summary of the PCI, SCSI, and RAID performance benefits. It also provides a summary of the Testability, Integration, and Reliability benefits.

  • Page 23: Raid Performance

    Number of drives: 30 maximum (10 to 15 drives in typical application) • Supports RAID levels 0, 1, 3, 5, 10 and JBOD 1.5.4 Testability • Access to all SCSI signals through programmed I/O • SCSI loopback diagnostics • SCSI bus signal continuity checking • Single-step mode operation LSI53C1510 Benefits Summary...

  • Page 24: Integration

    1.5.5 Integration • Dual Channel SCSI Multifunction Controller • 3.3 V/5 V PCI interface • Full 32-bit PCI DMA bus master • High-performance SCSI cores • Integrated SCSI SCRIPTS processors • ARM7TDMI 32-bit RISC processor • RAID PAE • O Message Unit 1.5.6 Reliability •...

  • Page 25: Applications

    LSI53C1510. All of the major functional blocks of RAID controller including processor, memory controller, XOR engine, and SCSI controllers are integrated into the LSI53C1510. This greatly reduces the amount of board space Applications 1-11...

  • Page 26: Host Adapter Board Application

    Because the LSI53C1510 supports both RAID and non-RAID operational modes, it gives the motherboard designer the option of building a base motherboard that uses the LSI53C1510 as a dual channel Ultra2 SCSI controller. The additional memory and real time clock required for RAID operation can then be provided on an optional RAID upgrade card that plugs into a connector mounted on the motherboard.

  • Page 27: Functional Description

    LSI53C1510 local memory. The LSI53C1510 uses a 32-bit PCI interface for communication with the host CPUs and system memory. The host interface to the LSI53C1510 is designed to minimize the amount of PCI bandwidth required to support I/O requests.

  • Page 28: Modes Of Operation

    In intelligent mode, the LSI53C1510 functions as an embedded RAID controller on a motherboard or as an add-in RAID host adapter board. In nonintelligent mode the LSI53C1510 functions as a PCI to SCSI dual channel wide Ultra2 controller. These modes are entered during the initialization of the LSI53C1510 on power-up.

  • Page 29: Lsi53C1510 Overview

    Flash ROM/DRAM EEPROM Bus Memory Bus Figure 2.1 illustrates the major components of the LSI53C1510 controller. A dual channel PCI interface function block provides slave access steering between the two SCSI cores when operating in nonintelligent mode. The Slave Access and Messaging Unit utilizes a FIFO for fast host system service and for speed matching between the 33 MHz domain of the PCI bus and the 40 MHz clock domain of the memory controller.

  • Page 30: Configuration And Initialization

    Memory 0 Base Address registers. The PAE accesses data and parity in the LSI53C1510 local memory and performs XOR operations to generate parity and data blocks. Multiple sources can be specified for each operation and multiple operations can be queued within the unit.

  • Page 31: Rom Size Configurations

    Table 2.2 ROM Size Configurations MEM_ADDR [3:0] Options 0000 16 Kbytes ROM Size (No external pull-ups) 0001 32 Kbytes ROM Size 0010 64 Kbytes ROM Size 0011 128 Kbytes ROM Size 0100 256 Kbytes ROM Size 0101 512 Kbytes ROM Size 0110 1024 Kbytes ROM Size 0111...

  • Page 32: I2O Overview

    Services Module (OSM), that resides on and interfaces to the host OS; and the Hardware Device Module (HDM), that resides on and interfaces with the LSI53C1510 adapter to be managed by the driver. The HDM and the Intermediate Service Module (ISM) are often referred to collectively as DDMs.

  • Page 33: I2O Benefits

    The I O operating environment of the LSI53C1510 provides two main advantages. First, it enables the system vendor, LSI Logic, to create an I/O platform that can support a number of intelligent configurations. The second advantage is the capability of stacked drivers, that enable a third party software vendor to provide value added expansion capability, independent of both the OS and the hardware.

  • Page 34: The I2O Communications Model

    O message and dispatches it to the LSI53C1510 for processing. Upon completion of the request, the LSI53C1510 dispatches the result back to the OSM by sending a message through the I O Message Layer. To the host OS, the OSM appears just like any other device driver.
  • Page 35 Request Message Frames into. This is the default method (Push model) for Request Message Frame transport, where the host itself copies the Request Message Frame into the LSI53C1510 local memory. To support shared memory access (read/write), the LSI53C1510...

  • Page 36: Hardware Messaging Unit

    Figure 2.3 Hardware Messaging Unit Protocol Engine PCI Interface External Memory Request Free List FIFO Control Request Free List FIFO Data Request Post List FIFO Control Request Post List FIFO Data Reply Free List FIFO Control Reply Free List FIFO Data Reply Post List FIFO Control Reply Post List FIFO Data Shared Memory...

  • Page 37: The Host Interface

    LSI53C1510 initialization. The default, power-up configuration, places Request messages in PCI shared memory local to the LSI53C1510. As an option, the Request messages can reside in host memory. The Reply messages, however, always reside in host memory. The Host Interface...

  • Page 38: Request Message

    The Post List FIFOs contain pointers to memory locations which contain new messages. The presence of a MFA in the Post FIFO indicates to the host or to the LSI53C1510 that a message is pending. The depth of the FIFOs determines the number of outstanding Request Messages which may be pending.
  • Page 39 LSI53C1510 is analogous to “pushing” messages down the PCI hierarchy to the LSI53C1510. This process may be referred to as the Push model. Alternatively, the LSI53C1510 may be configured to provide MFAs to memory located on the host.

  • Page 40: Reply Message

    2.2.4.1 To Send a Reply Message Figure 2.5 illustrates the LSI53C1510 Reply Message Transport. 1. The LSI53C1510 retrieves a MFA to the next free message frame from the Reply Message Free FIFO. 2. The LSI53C1510 then writes the message to the Reply Message frame queue.

  • Page 41: Lsi53C1510 Reply Message Transport

    3. When the Reply Message is written into the queue, the LSI53C1510 writes the pointer into the LSI53C1510 Post FIFO. 4. The LSI53C1510 Protocol Engine causes an interrupt to the host when the Reply Message is posted. 5. The host driver reads the Reply Register to retrieve the Reply Message pointer from the Post FIFO.

  • Page 42: Lsi53C1510 Protocol Engine

    2.3 LSI53C1510 Protocol Engine The LSI53C1510 provides a Protocol Engine to manage the execution of various I O protocols. The Protocol Engine offloads the host processor from management of the I O protocol by providing a higher level of abstraction for the SCSI protocols. This abstraction allows multiple SCSI protocols to operate simultaneously, with no coordination required between the host-based drivers.

  • Page 43: Supported Random Block Storage Messages

    In addition to the base messages for each class, the class definitions also provide utility messages to allow for management and configuration of devices. A generic user interface scripting language is used to allow for building generic configuration and management applications. LSI53C1510 Protocol Engine 2-17...

  • Page 44: Support Components

    2.4 Support Components The memory controller block within the LSI53C1510 provides access to external local memory resources. External memory devices supported include Flash ROM, DRAM, and SRAM. The sections below provide guidance in choosing the support components necessary for a fully functional implementation using the LSI53C1510.

  • Page 45: Dram Memory

    2.4.1 DRAM Memory The DRAM memory stores a run time image of the LSI53C1510 software. This memory also provides a data cache for RAID operations. The LSI53C1510 uses a 32-bit demultiplexed memory bus to access the DRAM. This memory bus has the capability to address up to 128 Mbytes of EDO DRAM.
  • Page 46 2-20 Functional Description...

  • Page 47: Software Description

    3.1 PCI RAID Software Solutions The LSI53C1510 is the first in high-integration RAID processor. LSI Logic offers a full PCI RAID software solution consisting of the LSI Logic RAID DDM, SYMplicity Storage Manager utility, and Wind River Systems’ IxWorks RTOS. These applications run in the LSI53C1510 intelligent mode.

  • Page 48: Symplicity Storage Manager

    3.1.2 SYMplicity Storage Manager SYMplicity Storage Manager provides host-based, transparent management of disk array controllers and the following features. • Common Features – Obtaining a RAID Module Profile – Naming a RAID Module (user-defined) – Locating a RAID Module • Configuration –...

  • Page 49: Wind River Systems' Ixworks Rtos

    3.1.3 Wind River Systems’ IxWorks RTOS Wind River Systems has ported IxWorks to the LSI53C1510. This version of IxWorks has been tuned for optimal performance. 3.2 Management Software Features Management software has the following features: • Supported by SYMplicity Storage Manager •...

  • Page 50: Raid Levels 0, 1, 3, 5, And

    3.3.1.2 RAID Level Indicates the way the controller reads and writes data and array parity on the drives. The LSI53C1510 controller can create RAID Level 0, 1, 3, and 5 logical units. These levels DO NOT indicate any certain hierarchy or preference.

  • Page 51: Caching

    3.3.1.5 RAID Level 3 RAID Level 3 adds parity to a striped array, permitting user data to be regenerated in the event of a failure. RAID Level 3 arrays use normal disk mechanisms for failure detection and the parity for data regeneration in the event of a failure.

  • Page 52: Hardware Assisted Parity Calculation

    3.3.4 Hardware Assisted Parity Calculation RAID firmware uses the Hardware PAE in the LSI53C1510 to offload parity generation and checking from the host. The PAE calculates the parity for write operations much faster than what can be done in software/firmware. It also allows multiple parity operations to be queued for maximum efficiency.

  • Page 53: Hot Swap Drive With Automatic, Transparent Reconstruction

    3.3.7 Hot Swap Drive with Automatic, Transparent Reconstruction This disk drive replaces a failed drive. Hot Swap technology makes it possible to remove and replace an array component while power is applied and data activity to and from the system continues. The controller automatically reconstructs data on the new drive, or initiates copying back the data from the global hot spare drive that is standing in for the failed drive.

  • Page 54: Battery Backup Support And Cache Recovery

    SCSI device access, and the creation of new applications. 3.5 Memory Requirements To run the LSI53C1510 in intelligent mode, with the PCI RAID software solutions (LSI Logic RAID DDM, SYMplicity Storage Manager utility, and Wind River Systems’ IxWorks RTOS), your memory should meet the following requirements.
  • Page 55 • NVRAM (with real time clock) - 8 Kbytes (equivalent to SGS-Thomson MK48T18) To run the LSI53C1510 in nonintelligent mode, with LSI Logic the SDMS software package, your memory should meet the following requirements. • Two Serial EEPROM - 2 Kbytes •...
  • Page 56 3-10 Software Description...

  • Page 57: Signal Descriptions

    Chapter 4 Signal Descriptions This chapter presents the LSI53C1510 pin configuration and signal definitions using tables and illustrations. Figure 4.1 is the functional signal grouping. The signal descriptions are organized into functional groups: • Section 4.1, “Signal Groupings,” page 4-2 •...

  • Page 58: Signal Groupings

    4.1 Signal Groupings The LSI53C1510 signals fall into the following groups. These groups are illustrated in Figure 4.1. • PCI Interface Signals – System Signals – Address and Data Signals – Interface Control Signals – Arbitration Signals – Interrupt Signals –...

  • Page 59: Lsi53C1510 Functional Signal Groupings

    Figure 4.1 LSI53C1510 Functional Signal Groupings LSI53C1510 A_SD[15:0] / System RST/ A_SDP[1:0] / A_SC_D / A_SI_O / Address PCI_AD[31:0] A_SMSG / C_BE[3:0]/ Data A_SREQ / A_SCTRL/ SCSI LVD A_SACK / Channel A_SBSY / FRAME/ A_SATN / TRDY/ A_SRST / IRDY/...

  • Page 60: Pci Interface Signals

    4.2 PCI Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Interrupt Signals, the Signal, Error Recording Signals, the Power Management Signal, and GPIO Interface...

  • Page 61: Address And Data Signals

    4.2.2 Address and Data Signals Table 4.3 describes the Address and Data signals. Table 4.3 Address and Data Signals Name Bump Type Strength Description PCI_AD[31:0] M25, M24, M26, 16 mA Physical dword PCI Address and Data are L25, L24, L26, K23, multiplexed on the same PCI pins.

  • Page 62: Interface Control Signals

    4.2.3 Interface Control Signals Table 4.4 describes the Interface Control signals. Table 4.4 Interface Control Signals Name Bump Type Strength Description FRAME/ S/T/S 16 mA Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to indicate that a bus transaction is beginning.

  • Page 63: Arbitration Signals

    This interrupt can be rerouted to INTA/ at power-up using the INTA/ enable sense resistor (pull-down on MEM_ADDR9). This causes the LSI53C1510 to program the SCSI Function B PCI register Interrupt Pin (3D) to 0x01. In intelligent mode, this signal is not used.

  • Page 64: Arm Signal

    4.2.6 ARM Signal Table 4.7 describes the ARM signal. Table 4.7 ARM Signal Name Bump Type Strength Description XINT – External Interrupt. This pin, when asserted, indicates that an interrupting condition is pending. 4.2.7 Error Recording Signals Table 4.8 describes the Error Recording signals. Table 4.8 Error Recording Signals Name...

  • Page 65: Gpio Interface Signals

    4.2.9 GPIO Interface Signals Table 4.10 describes the GPIO Interface signals. Table 4.10 GPIO Interface Signals Name Bump Type Strength Description A_GPIO [4:0] W24, 24 mA A General Purpose I/O. Signals GPIO0–GPIO3 V26, V25, default to input mode on reset. Signal GPIO4 defaults V24, U26 to output mode on reset.

  • Page 66: Scsi Interface Signals

    4.3 SCSI Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the following signal groups: the SCSI Clock Signal, SCSI A-Channel Interface Signals, and SCSI B-Channel Interface Signals. 4.3.1 SCSI Clock Signal Table 4.11 describes the SCSI Clock signal. Table 4.11 SCSI Clock Signal Name...
  • Page 67 Table 4.12 SCSI A-Channel Interface Signals (Cont.) Name Bump Type Strength Description A_SD[15:0]+/ AA24, Y26, W25, 48 mA SCSI Function A Data. W23, AE15, AF15, SCSI LVD Mode: A_SD[15:0]+/ signals are the AD16, AC17, AC22, positive half of the LVDlink 16-bit pair of AD22, AD23, AC24, SCSI data lines.
  • Page 68 Table 4.12 SCSI A-Channel Interface Signals (Cont.) Name Bump Type Strength Description A_SREQ / AE18, AE17 48 mA Request. This signal is a data handshake SCSI line from a target device. The target asserts this signal when requesting a data transfer.

  • Page 69: Scsi B-Channel Interface Signals

    4.3.3 SCSI B-Channel Interface Signals Table 4.13 describes the SCSI B-Channel Interface signals. Table 4.13 SCSI B-Channel Interface Signals Name Bump Type Strength Description B_SD[15:0]−/ AE11, AD11, 48 mA SCSI Function B Data. AF13, AD12, SCSI LVD Mode: B_SD[15:0]−/ signals are the W1, Y2, W3, negative half of the LVDlink 16-bit pair of AA1, AE6, AD6,...
  • Page 70 Table 4.13 SCSI B-Channel Interface Signals (Cont.) Name Bump Type Strength Description B_SC_D / AA3, AC1 48 mA Control/Data. The target asserts this signal SCSI with the MSG/ and C_D signals to determine the information transfer phase. B_SI_O / AA2, Y3 48 mA Input/Output.

  • Page 71: Memory Interface Signals

    4.4 Memory Interface Signals The Memory Interface Signals section contains tables describing the signals for the following groups: ROM/SRAM Interface Signals, SCAN Signals, and DRAM Interface Signals. 4.4.1 ROM/SRAM Interface Signals Table 4.14 describes the ROM/SRAM Interface signals. Table 4.14 ROM/SRAM Interface Signals Name Bump...

  • Page 72: Scan Signals

    4.4.2 SCAN Signals Table 4.15 describes the SCAN signals. Table 4.15 SCAN Signals Name Bump Type Strength Description SCANMODE Scan Mode Enable. Used for manufacturing test. SCAN_EN Scan Enable. Used for manufacturing test. SCAN_RAM_EN Scan RAM Enable. Used for manufacturing test. SCAN_RST_EN Scan Reset Enable.

  • Page 73: Dram Interface Signals

    4.4.3 DRAM Interface Signals Table 4.16 describes the DRAM Interface signals. Table 4.16 DRAM Interface Signals Name Bump Type Strength Description DRAM_CASFB_A DRAM Column Address Strobe Feedback. DRAM_CASFB_B DRAM Column Address Strobe Feedback. DRAM_WE/ 24 mA DRAM Write Enable. Indicates the direction data is to be transferred to/from DRAM.

  • Page 74: Miscellaneous Interface Signals

    4.5 Miscellaneous Interface Signals The Miscellaneous Interface Signals section contains tables describing the signals for the following signal groups: UART Interface Signals, JTAG Interface Signals, ARM Debug Interface Signals, the RAID Interface Signal Power and Ground Signals. 4.5.1 UART Interface Signals Table 4.17 describes the UART Interface signals.

  • Page 75: Arm Debug Interface Signals

    Table 4.18 JTAG Interface Signals (Cont.) Name Bump Type Strength Description TEST_HSC AC14 Test HSC. For test purposes only. TEST_DRAMCLK E2 Test DRAM Clock. For test purposes only. 4.5.3 ARM Debug Interface Signals Table 4.19 describes the ARM Debug Interface signals. Table 4.19 ARM Debug Interface Signals Name...

  • Page 76: Power And Ground Signals

    4.5.5 Power and Ground Signals Table 4.21 describes the signals for the Power and Ground signals. Table 4.21 Power and Ground Signals Name Bump Type Strength Description D6, D11, D16, Power for PCI bus drivers/receivers, SCSI D21, F4, F23, L4, bus drivers/receivers, local memory L23, T4, T23, interface drivers/receivers, and other I/O...

  • Page 77: Registers (Nonintelligent Mode)

    Section 5.3, “Differences from the LSI53C895 and the LSI53C896,” page 5-26 After power-on, the LSI53C1510 is configured as either a nonintelligent or intelligent controller. This chapter describes the PCI and host interface registers that are visible to the host in nonintelligent mode. In nonintelligent mode the LSI53C1510 operates similar to the LSI53C896 product.

  • Page 78: Lsi53C1510 Block Diagram In Nonintelligent Mode

    Flash ROM/DRAM EEPROM Bus Memory Bus This section contains descriptions of the LSI53C1510 PCI and host interface commands and registers. In the descriptions the term “set” is used to refer to bits that are programmed to a binary one. Similarly, the terms “clear”...

  • Page 79: Pci Functional Description (Nonintelligent Mode)

    5.1 PCI Functional Description (Nonintelligent Mode) In nonintelligent mode, the LSI53C1510 implements two PCI to Wide Ultra2 SCSI controllers in a single package. This configuration presents only one load to the PCI bus and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
  • Page 80 Address/Data bus during the PCI address phase. If there is a match of the upper 24 bits, the access is for the LSI53C1510 and the low order eight bits to define the register to be accessed. A decode of C_BE/[3:0] determines which registers and what type of access is to be performed.

  • Page 81: Pci Bus Commands And Functions Supported

    Yes (defaults to 0110) 1111 Memory Write and Invalidate Yes (defaults to 0111) 5.1.2.1 Interrupt Acknowledge Command The LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. PCI Functional Description (Nonintelligent Mode)
  • Page 82 5.1.2.2 Special Cycle Command The LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. 5.1.2.3 I/O Read Command The LSI53C1510 uses the I/O Read command to read data from an agent mapped in I/O address space.
  • Page 83 5.1.2.9 Configuration Write Command The LSI53C1510 uses the Configuration Write command to transfer data to the configuration space of each agent. An agent is selected when its IDSEL signal is asserted and AD[1:0] are 00. During the address phase of a configuration cycle, the AD[7:2] lines address the 64 Dword registers...
  • Page 84 Latency – In accordance with the PCI specification, the latency timer is ignored when issuing a Memory Write and Invalidate command such that when a latency time-out occurs, the LSI53C1510 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership.

  • Page 85: Internal Arbiter

    PCI Target Disconnect – During a Memory Write and Invalidate transfer, if the target device issues a disconnect the LSI53C1510 relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip issues the appropriate command on the next ownership, in accordance with the PCI specification.

  • Page 86: Pci Configuration Registers (Nonintelligent Mode)

    000b, and SCSI Function B by a value of 001b. Each SCSI function contains the same register set with identical default values, except the Interrupt Pin register. All PCI compliant devices, such as the LSI53C1510, must support the Vendor Device ID, Command, and Status registers.
  • Page 87 Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C1510 is logically disconnected from the PCI bus for all accesses except configuration accesses. Reserved [15:9] PCI Configuration Registers (Nonintelligent Mode)
  • Page 88 Write and Invalidate commands on the PCI bus. Reserved Enable Bus Mastering This bit controls the ability of the LSI53C1510 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1510 to behave as a bus master.
  • Page 89 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the LSI53C1510 whenever it detects a data parity error, even if the data parity error handling is disabled.
  • Page 90 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C1510 supports a value of 01b. Data Parity Error Reported This bit is set when the following conditions are met: •...
  • Page 91 Register: 0x08 Revision ID (Rev ID) Read Only Revision ID [7:0] This register specifies a device specific revision identifier. This silicon version of the LSI53C1510 is set to 0x00 for Rev A silicon. Registers: 0x09–0x0B Class Code Read Only Class Code...
  • Page 92 PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C1510 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C1510.
  • Page 93 This 8-bit register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. Since the LSI53C1510 is a multifunction controller the value of this register is 0x80. Register: 0x0F Not Supported Registers: 0x10–0x13...
  • Page 94 [31:0] This base register is used to map the SCRIPTS RAM into memory space. The LSI53C1510 requires 4 K of address space for this base register. This register has bits [11:0] hardwired to 000000000000. For detailed information on the operation of this register, refer to the PCI 2.1 Specification.
  • Page 95 If the external serial EEPROM interface is disabled (MEM_ADDR7 pulled HIGH), this register returns a value of 0x1000 (LSI Logic Vendor ID). The 16-bit value that should be stored in the external serial EEPROM for this register is the vendor’s PCI Vendor ID and must be obtained from the PCI SIG.
  • Page 96 Registers: 0x2E–0x2F Subsystem ID Read Only Default : If MEM_ADDR7 is HIGH Default : If MEM_ADDR7 is LOW Subsystem ID [15:0] This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and...
  • Page 97 Expansion ROM Base Address register with all ones and then reading back the register. The SCSI functions of the LSI53C1510 respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size.
  • Page 98 Register: 0x3C Interrupt Line Read/Write Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to.
  • Page 99 Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 SCSI function sets this register to 0x08. Register: 0x40...
  • Page 100 VER[2:0] PMES[4:0] PME_Support [15:11] Bits [15:11] define the power management states in which the LSI53C1510 will assert the PME pin. These bits are all set to zero. D2_Support D2 power management state is not supported. D1_Support D1 power management state is not supported.
  • Page 101 Version 1.0 of the PCI Power Management Specification. Registers: 0x44–0x45 Power Management Control/Status Read/Write PST DSCL[1:0] DSLT PWS[1:0] PME_Status This bit defines if the LSI53C1510 has generated a Power Management Event. DSCL[1:0] Data_Scale [14:13] These bits are not used in the LSI53C1510. DSLT Data_Select [12:9] These bits are not used in the LSI53C1510.

  • Page 102: Differences From The Lsi53C895 And The Lsi53C896

    The LSI53C1510 SCSI cores are similar to the LSI53C895 and LSI53C896, but there are differences. The differences are listed below. • FIFO Depth The LSI53C1510 SCSI DMA FIFOs are 816 bytes deep (the same as the LSI53C895). The LSI53C896 FIFOs are 944 bytes deep. • SCRIPTS RAM The LSI53C1510 SCRIPTS RAMs are 4 Kbytes while the LSI53C896 are 8 Kbytes.

  • Page 103: Registers (Intelligent Mode)

    • Section 6.4, “Shared Memory,” page 6-27 After power-on, the LSI53C1510 is configured as either a nonintelligent or intelligent controller. This chapter describes the PCI and host interface registers that are visible to the host in intelligent mode. In intelligent mode, the LSI53C1510 is configured as an Intelligent IOP supporting...

  • Page 104: Lsi53C1510 Block Diagram In Intelligent Mode

    Flash ROM/DRAM EEPROM Memory Bus This section contains descriptions of the LSI53C1510 PCI and host interface commands and registers. In the descriptions the term “set” is used to refer to bits that are programmed to a binary one. Similarly, the terms “clear”...

  • Page 105: Programming Models

    6.1 Programming Models The LSI53C1510 in intelligent mode contains two programming models: a System (host) Programming Model and a Local Programming Model. The system model includes all necessary hardware registers, shared memory and associated memory addresses from the host viewpoint using system addresses.

  • Page 106: Pci Configuration Registers (Intelligent Mode

    IDSEL pin asserted and the appropriate value in AD[10:8] during the address phase of the transaction. All PCI compliant devices, such as the LSI53C1510, must support the Vendor Device ID, Command, and Status registers.
  • Page 107 PCI cycles. When a zero is written to this register, the LSI53C1510 is logically disconnected from the PCI bus for all accesses except configuration accesses. PCI Configuration Registers (Intelligent Mode)
  • Page 108 PCI bus. Reserved Enable Bus Mastering This bit controls the ability of the LSI53C1510 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1510 to behave as a bus master.
  • Page 109 For instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the LSI53C1510 whenever it detects a data parity error, even if data parity error handling is disabled.
  • Page 110 A value of one implements a list of extended capabilities. Reserved [3:0] Register: 0x08 Revision ID (Rev ID) Read Only Revision ID [7:0] This register specifies a device specific revision identifier. This silicon version of the LSI53C1510 is set to 0x00 for Rev A silicon. Registers (Intelligent Mode)
  • Page 111 The value of this register is 0x0E0000, which identifies an I O IOP (LSI53C1510 in intelligent mode). Register: 0x0C Cache Line Size Read/Write...
  • Page 112 The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C1510 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C1510.
  • Page 113 [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C1510 requires 256 bytes of I/O space for this base address register. This register has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space.
  • Page 114 Registers: 0x14–0x17 Base Address Register One (Shared MEMORY) Read/Write BARO[31:0] BARO MEMORY Base Address Register One [31:0] This base address register map indicates width (32-bit) and location of memory required by the device and its size is programmable from 1 K (2 ) through 128 M (2 bytes in steps of powers of 2.
  • Page 115 Registers: 0x2E–0x2F Subsystem ID Read Only Subsystem ID [15:0] This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID).
  • Page 116 Register: 0x34 Capabilities Pointer Read Only Capabilities Pointer [7:0] This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration. Registers: 0x35–0x3B Reserved Register: 0x3C Interrupt Line Read/Write Interrupt Line [7:0] This register is used to communicate interrupt line routing information.
  • Page 117 Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 sets this register to 0x1E. Register: 0x3F Max_Lat Read Only...
  • Page 118 (0x01). Register: 0x41 Next Item Pointer Read Only Next_Item_Ptr [7:0] The LSI53C1510 has these bits set to zero indicating PCI does not have any further PCI extended capabilities registers. Registers: 0x42–0x43 Power Management Capabilities (PMC) Read Only PMES[4:0]...
  • Page 119 1.0. Registers: 0x44–0x45 Power Management Control/Status (PMCSR) Read/Write PST DSCL[1:0] DSLT PWS[1:0] PME_Status Bit 15 defines if the LSI53C1510 has generated a Power Management Event. DSCL[1:0] Data_Scale [14:13] Bits [14:13] are not supported in the LSI53C1510. DSLT Data_Select [12:9] Bits [12:9] are not supported in the LSI53C1510.
  • Page 120 [7:2] PWS[1:0] Power State [1:0] Bits [1:0] are used to determine the current power state of the LSI53C1510. They are also used to set the LSI53C1510 to a new power state. Power states are defined as: 00b00 0b11 D3 hot...

  • Page 121: Host Interface Registers (Intelligent Mode)

    6.3 Host Interface Registers (Intelligent Mode) The host interface contains the following registers as shown in Table 6.2. Reserved registers and bits are shaded. Table 6.2 LSI53C1510 Host Interface Register Map 16 15 0 Address Page DiagINT 0x00 6-20 WRSEQ...
  • Page 122 This register is intended for diagnostic/test use only. The DiagINT register contains interrupt status and control as described below. The LSI53C1510 Protocol Engine can be configured to generate interrupts using direct F/W control. This register is used to report and enable/mask interrupts to PCI.
  • Page 123 Register: 0x04 WRSEQ Write Only KEY_VALUE Note: This register is intended for diagnostic/test use only. The WRSEQ register is used to enable write accesses to the DIAG register. In order to prevent inadvertent access, the DIAG register cannot be written to unless a specific sequence of data is written to the WRSEQ register.
  • Page 124 Reset Adapter (write only) This write only bit will cause the Protocol Engine reset controller to generate a soft reset to all LSI53C1510 logic. This bit will be automatically cleared when the soft reset condition is generated. The ARM core will start executing from its Reset Vector when the soft reset condition subsides.
  • Page 125 DMMAP Diagnostic Memory Map This bit when set causes all PCI accesses to Memory Base 0 address space (except for offsets 0x00–0x7F) to be mapped to internal local bus accesses. This allows Host utilities the capability to read or write any arbitrary internal local address.
  • Page 126 Register: 0x20 Host Doorbell Read/Write Host Doorbell [31:0] This is a 32-bit inbound doorbell register accessible by the host. All 32 bits of the register are read/write by a PCI master, although the PCI master can only set a bit to one. The PCI master cannot clear a bit to zero.
  • Page 127 Message is available for the host to process (ReplyPostFIFO not empty and prefetch of ReplyPost- MFA complete). This bit will cause a PCI interrupt to be generated when ReplyIntMask = 0. This is the default interrupt reporting mechanism for the LSI53C1510 Protocol Engine. Reserved [2:0]...
  • Page 128 Reply Free List FIFO (Write Only) FIFO Reply messages are used by the LSI53C1510 to send status information back to the host. For a complete explanation of how the Reply Post/Free List FIFOs are used in the message passing I/O interface, see Section 2.2, “The Host Interface.”...

  • Page 129: Shared Memory

    6.4 Shared Memory A region of Shared Memory (LSI53C1510 local memory mapped to System Addresses) is provided to allow the host to write Request Message Frames into. This is the default method (Push model) for Request Message Frame transport, where the host itself copies the Request Message Frame into the LSI53C1510 local memory.
  • Page 130 6-28 Registers (Intelligent Mode)

  • Page 131: Dc Characteristics

    Section 7.5, “SCSI Timing Diagrams,” page 7-36 • Section 7.6, “Pinouts and Packaging,” page 7-43 7.1 DC Characteristics 34.732 pc This section of the manual describes the LSI53C1510 DC characteristics. Table 7.1 through Table 7.13 give current and voltage specifications.

  • Page 132: Absolute Maximum Stress Ratings

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.1 Absolute Maximum Stress Ratings Symbol Parameter Unit Test Conditions −55 °C Storage temperature – −0.5 Supply voltage – −0.3 Input voltage +0.3 – −0.3 Input voltage (5 V tolerant pins) 5.25 –...

  • Page 133: Lvd Driver

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Units Test Conditions Source (+) current Asserted state − −7 −11 Sink (−) current Asserted state...

  • Page 134: Lvd Receiver

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.2 LVD Receiver − − − − Table 7.5 DIFFSENS SCSI Signal Symbol Parameter Unit Test Conditions HVD sense voltage Note 1 LVD sense voltage Note 1 −0.3 SE sense voltage Note 1...

  • Page 135: Bidirectional Signals—Gpio0, Gpio1, Gpio2, Gpio3 Gpio4

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.8 Bidirectional Signals—GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 Symbol Parameter Unit Test Conditions Input high voltage – −0.3 Input low voltage – −8 mA dynamic Output high voltage Output low voltage 8 mA dynamic −10...

  • Page 136: Input Signals—Clk, Gnt/, Idsel, Rst/, Sclk, Tck Tdi, Test_Hsc, Test_Rstn, Tms

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.11 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC TEST_RSTN, TMS Symbol Parameters Unit Test Conditions Input high voltage 0.5 V – −0.3 Input low voltage 0.3 V –...

  • Page 137: Tolerant Technology Electrical Characteristics

    34.5 pc 4.333 pc 7.2 TolerANT Technology Electrical Characteristics The LSI53C1510 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.

  • Page 138: Rise And Fall Time Test Condition

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.14 TolerANT Technology Electrical Characteristics for SE SCSI Signals Symbol Parameter Units Test Conditions Rise time, 10% to 90% 18.5 Figure 7.3 Fall time, 90% to 10% 18.5 Figure 7.3 Slew rate LOW to HIGH...

  • Page 139: Hysteresis Of Scsi Receivers

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.5 Hysteresis of SCSI Receivers Input Voltage (Volts) Figure 7.6 Input Current as a Function of Input Voltage 44.25 pc 14.4 V 8.2 V − 0.7 V HIGH-Z OUTPUT −20...

  • Page 140: Output Current As A Function Of Output Voltage

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.7 Output Current as a Function of Output Voltage −200 −400 −600 −800 Output Voltage (Volts) Output Voltage (Volts) 44.25 pc 48.583 p 7-10 Specifications 52.5 pc...

  • Page 141: Ac Characteristics

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to the Section 7.1, “DC Characteristics”). Chip timing is based on simulation at worst case voltage, temperature, and processing.

  • Page 142: Reset Input

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.16 Figure 7.9 provide Reset Input data. Table 7.16 Reset Input Symbol Parameter Units Reset pulse width – Reset deasserted setup to CLK HIGH – MEM_ADDR setup time to CLK HIGH –...

  • Page 143: Interrupt Output

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.17 Figure 7.10 provide Interrupt Output data. Table 7.17 Interrupt Output Symbol Parameter Units CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH IRQ/ deassertion time –...

  • Page 144: Pci And External Memory Interface Timing Diagrams

    Figure 7.11 through Figure 7.14 represent signal activity when the LSI53C1510 accesses the PCI bus. This section includes timing diagrams for access to four groups of memory configurations. The first group applies to Target Timing. The second group applies to Initiator Timing.

  • Page 145: Pci Configuration Register Read

    Byte Enable 44.25 pc (Driven by Master) (Driven by Master-Addr; LSI53C1510-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) DEVSEL/ (Driven by LSI53C1510) IDSEL (Driven by Master) 48.583 p PCI and External Memory Interface Timing Diagrams 7-15 52.5 pc...

  • Page 146: Pci Configuration Register Write

    Data In (Driven by Master) C_BE/ Byte Enable (Driven by Master) 44.25 pc (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) DEVSEL/ (Driven by LSI53C1510) IDSEL (Driven by Master) 48.583 p 7-16 Specifications...

  • Page 147: Operating Registers/Scripts Ram Read, 32-Bit

    C_BE/ Byte Enable (Driven by Master) 44.25 pc (Driven by Master-Addr; LSI53C1510-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) DEVSEL/ (Driven by LSI53C1510) 48.583 p PCI and External Memory Interface Timing Diagrams 7-17 52.5 pc...

  • Page 148: Operating Registers/Scripts Ram Write, 32-Bit

    Addr In Data In (Driven by Master) C_BE/ Byte Enable (Driven by Master) 44.25 pc (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) DEVSEL/ (Driven by LSI53C1510) 48.583 p 7-18 Specifications 52.5 pc...
  • Page 149 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc This page intentionally left blank. 44.25 pc 48.583 p PCI and External Memory Interface Timing Diagrams 7-19 52.5 pc...

  • Page 150: Initiator Timing

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.4.2 Initiator Timing Table 7.22 through Table 7.27 Figure 7.15 through Figure 7.20 describe Initiator timing. Table 7.22 Nonburst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time –...

  • Page 151: Nonburst Opcode Fetch, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.15 Nonburst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ Data (Driven by LSI53C1510) Data Addr Addr...

  • Page 152: Burst Opcode Fetch, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.23 Burst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time –...

  • Page 153: Burst Opcode Fetch, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.16 Burst Opcode Fetch, 32-Bit Address and Data (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by Data Data LSI53C1510) Addr (Driven by LSI53C1510- Addr;...

  • Page 154: Back-To-Back Read, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.24 Back-to-Back Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time –...

  • Page 155: Back-To-Back Read, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.17 Back-to-Back Read, 32-Bit Address and Data (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ Data (Driven by Data LSI53C1510) Addr Addr (Driven by LSI53C1510- Addr;...

  • Page 156: Back-To-Back Write, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.25 Back-to-Back Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid Side signal input setup time –...

  • Page 157: Back-To-Back Write, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.18 Back-to-Back Write, 32-Bit Address and Data (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) Data Addr Addr Data (Driven by LSI53C1510- Addr;...

  • Page 158: Burst Read, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.26 Burst Read, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid 44.25 pc 48.583 p 7-28...

  • Page 159: Burst Read, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.19 Burst Read, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C1510) GPIO1_MASTER/ (Driven by LSI53C1510) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/...

  • Page 160: Burst Write, 32-Bit Address And Data

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.27 Burst Write, 32-Bit Address and Data Symbol Parameter Unit Shared signal input setup time – Shared signal input hold time – CLK to shared signal output valid 44.25 pc 48.583 p 7-30...

  • Page 161: External Memory Timing

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.20 Burst Write, 32-Bit Address and Data (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) Addr Data Data (Driven by...
  • Page 162 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.28 DRAM Timing Parameters (Using 50 ns Extended Data Out Mode) Symbol Parameter Unit Access from column address – Tasc Common address setup – Tasr Row address setup –...

  • Page 163: Edo Dram Burst Read

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.21 EDO DRAM Burst Read M_CLK B_CLK D_SEL B_ A A0+1 A0+2 A0+3 A0+4 MEM_RA ROW 0 COL 0 COL 0+1 COL 0+4 COL 0+2 COL 0+3 nRAS nCAS 44.25 pc...

  • Page 164: Flash Rom Normal Read Only Mode

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.22 FLASH ROM Normal Read Only Mode 44.25 pc 48.583 p 7-34 Specifications 52.5 pc...

  • Page 165: Flash Rom Program/Verify Mode

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.23 FLASH ROM Program/Verify Mode 44.25 pc 48.583 p PCI and External Memory Interface Timing Diagrams 7-35 52.5 pc...

  • Page 166: Scsi Timing Diagrams

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.5 SCSI Timing Diagrams Table 7.29 through Table 7.39 Figure 7.24 through Figure 7.28 describe SCSI timing data. Table 7.29 Initiator Asynchronous Send Symbol Parameter Units SACK/ asserted from SREQ/ asserted –...

  • Page 167: Initiator Asynchronous Receive

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.30 Initiator Asynchronous Receive Symbol Parameter Units SACK/ asserted from SREQ/ asserted – SACK/ deasserted from SREQ/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted –...

  • Page 168: Target Asynchronous Send

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.31 Target Asynchronous Send Symbol Parameter Units SREQ/ deasserted from SACK/ asserted – SREQ/ asserted from SACK/ deasserted – Data setup to SREQ/ asserted – Data hold from SACK/ asserted –...

  • Page 169: Scsi-1 Transfers (Se 5.0 Mbytes)

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.33 SCSI-1 Transfers (SE 5.0 Mbytes) Symbol Parameter Units Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width – Receive SREQ/ or SACK/ assertion pulse width –...

  • Page 170: Scsi-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) Or 20.0 Mbytes (16-Bit Transfers) 40 Mhz Clock

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.35 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit transfers) or 20.0 Mbytes (16-Bit transfers) 40 MHz Clock Symbol Parameter Units Send SREQ/ or SACK/ assertion pulse width – Send SREQ/ or SACK/ deassertion pulse width –...

  • Page 171: Ultra Scsi Se Transfers 20.0 Mbytes (8-Bit Transfers) Or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 Mhz Clock

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.37 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width –...

  • Page 172: Initiator And Target Synchronous Transfer

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.39 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock Symbol Parameter Unit Send SREQ/ or SACK/ assertion pulse width –...

  • Page 173: Pinouts And Packaging

    38.25 pc 34.5 pc 4.333 pc 7.6 Pinouts and Packaging Figure 7.29 is pinout information for the LSI53C1510 388 BGA chip package. Table 7.40 provides the 388 BGA pin list by location and Table 7.41 provides the same pin list alphabetically.

  • Page 174: Left Half Of The Lsi53C1510 388 Bga Chip - Top View

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.29 Left Half of the LSI53C1510 388 BGA Chip - Top View DRAM_ DRAM_OE/ DRAM_ CORE3 DRAM_ DRAM_ DRAM_ DRAM_ DRAM_ DRAM_ DRAM_ ADD1 CASFB_A CAS5/ CAS3/...
  • Page 175 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.29 Right Half of the LSI53C1510 388 BGA Chip - Top View (Cont.) DRAM_ DRAM_ DRAM_ DRAM_ DRAM_ DRAM_ PCI_AD0 PCI_AD3 PCI_AD6 C_BE0 PCI_AD10 PCI_AD13 DATA23 DATA9...

  • Page 176: Signal Names And Bga Position

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.40 Signal Names and BGA Position Signal Signal Signal Signal Signal Name Name Name Name Name DRAM_ADDR11 DRAM_ADDR10 ARM_TRST/ B_SACK−/ DRAM_ADDR6 B_GPIO1 DRAM_ADDR1 B_RBIAS− B_GPIO0 DRAM_OE/ B_SD6−/ DRAM_ADDR0 B_GPIO2 DRAM_CASFB_A...

  • Page 177: Signal Names By Bga Position

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.41 Signal Names By BGA Position Signal Signal Signal Signal Signal Name Name Name Name Name B_SI_O+/ DRAM_DATA2 PCI_AD2 A_SACK−/ AC20 B_SMSG−/ DRAM_DATA3 PCI_AD3 A_SACK+/ AF21 B_SMSG+/ DRAM_DATA4 PCI_AD4 A_SATN−/...

  • Page 178: Lsi53C1510 388 Ball Grid Array

    3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.30 LSI53C1510 388 Ball Grid Array 44.25 pc 48.583 p 7-48 Specifications 52.5 pc...

  • Page 179: Pbga (Ii) Mechanical Drawing

    MD97.II Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code II. 48.583 p Pinouts and Packaging 7-49 52.5 pc...
  • Page 180 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 44.25 pc 48.583 p 7-50 Specifications 52.5 pc...

  • Page 181: Register Summary

    Appendix A Register Summary Table A.1 lists the LSI53C1510 PCI registers (nonintelligent mode) by register name. Table A.1 LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map Register Name Address Read/Write Page Base Address Register One (MEMORY) 0x14–0x17 Read/Write 5-18 Base Address Register Two (SCRIPTS RAM) 0x18–0x1B...

  • Page 182: A.2 Lsi53C1510 Pci Registers (Intelligent Mode) Register Map

    Table A.1 LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map (Cont.) Register Name Address Read/Write Page Min_Gnt 0x3E Read Only 5-23 Next Item Pointer 0x41 Read Only 5-24 Not Supported 0x0F – 5-17 Power Management Capabilities 0x42–0x43 Read Only 5-24 Power Management Control/Status 0x44–0x45...
  • Page 183 Table A.2 LSI53C1510 PCI Registers (Intelligent Mode) Register Map (Cont.) Register Name Address Read/Write Page Data 0x47 Read Only 6-18 Device ID 0x02–0x03 Read Only Expansion ROM Base Address 0x30–0x33 Read/Write 6-13 Header Type 0x0E Read Only 6-10 Interrupt Line...

  • Page 184: A.3 Lsi53C1510 Host Interface Registers (Intelligent Mode)

    Table A.3 lists the LSI53C1510 Host Interface Registers (intelligent mode) by register name. Table A.3 LSI53C1510 Host Interface Registers (Intelligent Mode) Register Name Address Read/Write Page Data 0x08 Read/Write 6-18 DiagINT 0x00 Read/Write 6-20 Host Doorbell 0x20 Read/Write 6-24 Reply Interrupt Mask...
  • Page 185 6-17 BIOS (PWS[1:0]) 5-26 6-18 bit 1 DISARM (disable ARM core) 6-22 (RID) 5-15 bridge support extensions (BSE[7:0]) 5-27 6-18 (RID[7:0]) BsaBlockRead 2-17 (RMA) 5-13 BsaBlockReassign 2-17 (RTA) 5-13 BsaBlockWrite 2-17 LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller IX-1...
  • Page 186 BsaBlockWriteVerify 2-17 DEVSEL/ BsaCacheFlush 2-17 timing 5-13 BsaDeviceReset 2-17 DiagINT/CLRINT (diagnostic interrupt (read)/ clear interrupt BsaMediaFormat 2-17 (write)) 6-20 BsaMediaVerify 2-17 DIFFSENS SCSI signals BsaPowerMgt 2-17 disk array BsaStatusCheck 2-17 burst opcode fetch 32-bits address and data 7-22 channel burst read 32-bits address and data 7-28 engine burst write 32-bits address and data...
  • Page 187 1-10 GNT/ latency grant timer 5-16 (LT[7:0]) 6-10 low voltage differential LSI53C1510 benefits hardware assisted parity calculation summary hardware parity assist engine features header type 5-17 6-10 modes high power differential overview host adapter board application...
  • Page 188 nonburst opcode fetch support (PMES[4:0]) 5-25 6-16 32-bits address and data 7-20 power fail 4-19 nonintelligent power management event controller power state (PWS[1:0]) 5-26 6-18 NVRAM POWER_FAIL/ 4-19 programming models protocol engine 2-16 push model 2-15 online dynamic capacity expansion RAID level migration/reconfiguration RAID 1-11...
  • Page 189 scan (Cont.) messages 2-17 mode enable 4-16 SYMplicity RAM enable 4-16 I2O RAID reset enable 4-16 software 2-16 test clock enable 4-16 storage manager SCAN_EN 4-16 system SCAN_RAM_EN 4-16 error SCAN_RST_EN 4-16 interface SCAN_TEST_CLK_EN 4-16 programming model SCAN_TRI_EN 4-16 signals SCANMODE 4-16 scatter/gather...
  • Page 190 4-20 VDD-A 4-20 vendor ID (VID[15:0]) version (VER[2:0]) 5-26 6-17 voltage feed-through protection 1-10 4-20 VSS-A 4-20 VSS-CORE 4-20 wide Ultra2 SCSI Wind River System IxWorks write and invalidate enable (WIE) 5-12 XINT zero wait-state IX-6 Index...
  • Page 191 Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller...
  • Page 192 LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSI53C1510 I O-Ready PCI RAID Ultra2 SCSI Controller Technical Manual. Place a check mark in the appropriate blank for each category. Excellent Good Average...
  • Page 193 U.S. Distributors by State A. E. Avnet Electronics Colorado Illinois Michigan http://www.hh.avnet.com Denver North/South Brighton B. M. Bell Microproducts, A. E. Tel: 303.790.1662 A. E. Tel: 847.797.7300 I. E. Tel: 810.229.7710 Inc. (for HAB’s) B. M. Tel: 303.846.3065 Tel: 314.291.5350 Detroit http://www.bellmicro.com W.
  • Page 194 U.S. Distributors by State (Continued) New York South Carolina Washington Hauppauge A. E. Tel: 919.872.0712 Kirkland I. E. Tel: 516.761.0960 W. E. Tel: 919.469.1502 I. E. Tel: 425.820.8100 Long Island Maple Valley South Dakota A. E. Tel: 516.434.7400 B. M. Tel: 206.223.0080 A.
  • Page 195 Direct Sales Representatives by State (Components and Boards) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 Tel: 512.794.9006 I. S. Infinity Sales, Inc. Arlington ION Associates, Inc. Tel: 817.695.8000 R. A. Rathsburg Associ- Houston ates, Inc. Tel: 281.376.2000 Synergy Associates, Utah...
  • Page 196 Sales Offices and Design Resource Centers LSI Logic Corporation Fort Collins New Jersey Canada Corporate Headquarters 2001 Danfield Court Red Bank Ontario Fort Collins, CO 80525 1551 McCarthy Blvd 125 Half Mile Road Ottawa Tel: 970.223.5100 Milpitas CA 95035 Suite 200 260 Hearst Way Tel: 408.433.8000...
  • Page 197 Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’...
  • Page 198 Switzerland Tel: 44.1793.849933 Bangalore, India 560078 Xicheng District ♦ Brugg Fax: 44.1793.859555 Tel: 91.80.664.5530 Beijing 100045, China LSI Logic Sulzer AG Tel: 86.10.6804.2534 to 38 Fax: 91.80.664.9748 Mattenstrasse 6a Fax: 86.10.6804.2521 ♦ CH 2555 Brugg Sales Offices with Israel Tel: 41.32.3743232...

Table of Contents