LSI LSI53C895A Technical Manual page 14

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6.15 External Clock
6.16 Reset Input
6.17 Interrupt Output
6.18 PCI Configuration Register Read
6.19 PCI Configuration Register Write
6.20 32-Bit Operating Register/SCRIPTS RAM Read
6.21 64-Bit Address Operating Register/SCRIPTS RAM Read
6.22 32-Bit Operating Register/SCRIPTS RAM Write
6.23 64-Bit Address Operating Register/SCRIPTS RAM Write
6.24 Nonburst Opcode Fetch, 32-Bit Address and Data
6.25 Burst Opcode Fetch, 32-Bit Address and Data
6.26 Back to Back Read, 32-Bit Address and Data
6.27 Back to Back Write, 32-Bit Address and Data
6.28 Burst Read, 32-Bit Address and Data
6.29 Burst Read, 64-Bit Address and Data
6.30 Burst Write, 32-Bit Address and Data
6.31 Burst Write, 64-Bit Address and 32-Bit Data
6.32 External Memory Read
6.33 External Memory Write
Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access
6.34
Read Cycle
Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access
6.35
Write Cycle
Slow Memory ( ≤ 128 Kbytes) Read Cycle
6.36
Slow Memory ( ≤ 128 Kbytes) Write Cycle
6.37
≤= 64 Kbytes ROM Read Cycle
6.38
≤ 64 Kbyte ROM Write Cycle
6.39
6.40 Initiator Asynchronous Send
6.41 Initiator Asynchronous Receive
6.42 Target Asynchronous Send
6.43 Target Asynchronous Receive
6.44 SCSI-1 Transfers (SE 5.0 Mbytes)
6.45 SCSI-1 Transfers (Differential 4.17 Mbytes)
6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 50 MHz Clock
Contents
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