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Description Of Sample Application - Renesas REJ06B0734-0100 Application Note

Data transfer to on-chip peripheral modules with dmac

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2.

Description of Sample Application

In this sample application, the DMAC and on-chip peripheral module requests are used to transfer data from external
memory to the SCIF.
2.1
Operational Overview of Modules Used
When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of
channels, and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC
are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable
as burst mode or cycle-stealing mode.
An overview of the DMAC is given in table 1. Also, a block diagram of the DMAC is shown in figure 1.
Table 1
Overview of DMAC
Item
Number of channels
Address space
Length of transfer data
Maximum transfer
count
Address mode
Transfer request
Bus mode
Priority level
Interrupt request
External request
detection
Transfer request
acknowledge
signal/transfer end
signal
Note: For details on the DMAC, refer to the section on the direct memory access controller in the
SH7263/SH7203 Group Hardware Manual.
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
Description
8 (CH0 to CH7)
Only 4 (CH0 to CH3) can receive external requests.
4 Gbytes
Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
16,777,216 (24 bits) transfers
Single address mode and dual address mode
Auto request, external request, and on-chip peripheral module request
• SH7203/SH7263
2
(SCIF: 8 sources, I
C3: 8 sources, ADC: 1 source, MTU2: 5 sources, CMT: 2
sources, USB: 2 sources, FLCTL: 2 sources, RCAN-TL1: 2 sources, SSI: 4
sources, SSU: 4 sources)
• SH7263
(SRC: 2 sources, ROM-DEC: 1 source, SDHI: 2 sources)
Cycle-stealing mode and burst mode
Channel priority fixed mode and round-robin mode
An interrupt request to the CPU is made when half or all of a transfer process is
completed.
DREQ input low/high level detection, rising/falling edge detection
Active levels for DACK and TEND can be set independently
December 2008
SH7263/SH7203 Group
Page 3 of 17

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Sh7263Sh7203