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2.2
Procedure for Setting Used Modules
This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from
memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart
of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware
Manual.
START
Set standby control register 2
(STBCR2)
Set DMA channel control register
(CHCRn)
Set DMA source address control
register (SARn)
Set DMA reload source
address register (RSARn)
Set DMA destination address
register (DARn)
Set DMA reload destination
address register (RDARn)
Set DMA transfer count register
(DMATCRn)
Set DMA reload transfer
count register (RDMATCRn)
Set DMA channel control register
(CHCRn)
Set DMA extension resource selector
registers (DMARS0 to DMARS3)
Set DMA operation register
(DMAORn)
Set DMA channel control register
(CHCRn)
END
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
• Enabling clock supply to the DMAC (STBCR2)
[1]
Clear the MSTP8 (module stop 8) bit to 0
[Function]
• Disabling DMA transfer (CHCRn)
[2]
Clear the DE (DMA enable) bit to 0
[Function]
[1]
• Setting DMA transfer source address (SARn)
[3]
[Function]
• Setting DMA transfer source reload address (RSARn)
[4]
[2]
[Function]
• Setting DMA transfer destination address (DARn)
[5]
[Function]
[3]
• Setting DMA transfer destination reload address (RDARn)
[6]
[Function]
• Setting the DMA transfer count (DMATCRn)
[7]
[Function]
[4]
• Setting the DMA transfer reload count (RDMATCRn)
[8]
[Function]
• Setting the DMA transfer mode (CHCRn)
[9]
Set the TC (transfer count mode) bit
[5]
[Function]
[6]
Set the RLDSAR (SAR reload function enable/disable) bit
[Function]
Set the RLDDAR (DAR reload function enable/disable) bit
[Function]
Set the DM (destination address mode) bits
[7]
[Function]
Set the SM (source address mode) bits
[Function]
[8]
Set the RS (resource select) bits to B'1000.
[Function]
Set the TB (transfer bus mode) bit
[9]
[Function]
Set the TS (transfer size) bits
[Function]
[10]
Set the IE (interrupt enable) bit
[Function]
• Specifying settings for DMA transfer requests from on-chip peripheral
[10]
modules (DMARS0 to DMARS3)
[11]
[Function]
• Setting the DMA operation register (DMAOR)
[11]
Read from the AE (address error flag) bit and then clear it to 0
[Function]
[12]
Read from the NMIF (NMI flag) bit and then clear it to 0
[Function]
Set the DME (DMA master enable) bit to 1
[Function]
• Enablling DMA transfer (CHCRn)
[12]
Set the DE (DMA enable) bit to 1
[Function]
Figure 2 Flowchart of Initializing DMAC
December 2008
SH7263/SH7203 Group
Clock supply to the DMAC
Disable DMA transfer
Specify DMA transfer source address
Specify DMA transfer source address to be reloaded
Specify DMA transfer destination address
Specify DMA transfer destination address to be reloaded
Set the DMA transfer count
Set the DMA transfer count to be reloaded
"0": Transfer data once for each transfer request
(When the SCIF or IIC3 is selected as the transfer
request source)
"1": Transfer data for the count specified in DMATCRn for
each transfer requests
Enables/disables reload function to SAR and DMATCR
Enables/disables reload function to DAR and DMATCR
Select whether the DMA transfer destination address is
incremented or decremented
Fix/increment/decrement the DMA transfer destination address
Select whether the DMA transfer source address is
incremented or decremented
Fix/increment/decrement the DMA transfer source address
Select DMA extension resource selector (DMA transfer
request source)
Select a DMA transfer bus mode.
Cycle-stealing mode/burst mode
Note: When TC is set to 0, select cycle-stealing mode
Specify the DMA transfer size
Enable/disable interrupt requests
Select the DMA transfer request source
SCIF, IIC3, A/D converter, MTU2, or CMT
Clear the address error flag
Clear the NMI flag
Enable DMA transfer on all the channels
Start DMA transfer
Page 5 of 17
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