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5. Sample Program Listing "main.c" (5)
217
bit6
218
bit5
219
bit4-3
220
bit2
221
bit1
222
bit0
223
*/
224
225
/* ----Setting DMA extension resource selector 0---- */
226
DMAC.DMARS0.BIT.CH1MID = 0x20;
227
DMAC.DMARS0.BIT.CH1RID = 0x01;
228
229
/* ----Setting DMA operation register---- */
230
DMAC.DMAOR.WORD &= 0xfff9u;
231
232
if(DMAC.DMAOR.BIT.DME == 0ul){
233
DMAC.DMAOR.BIT.DME = 1ul;
234
}
235
236
/* ----DMA transfer execution---- */
237
DMAC.CHCR1.BIT.DE = 1ul;
238 }
239 /*""FUNC COMMENT""*******************************************************
240 * Outline
: DMAC stop
241 *-----------------------------------------------------------------------
242 * Include
: #include "iodefine.h"
243 *-----------------------------------------------------------------------
244 * Declaration : void io_dma1_stop(void);
245 *-----------------------------------------------------------------------
246 * Function : Detects the end of DMA transfer and disables DMA transfer
247 *-----------------------------------------------------------------------
248 * Argument : void
249 *-----------------------------------------------------------------------
250 * Return Value: void
251 *-----------------------------------------------------------------------
252 * Notice
:
253 *""FUNC COMMENT END""***************************************************/
254 void io_dma1_stop(void)
255 {
256
/* Detecting end of transfer */
257
while(DMAC.CHCR1.BIT.TE == 0ul){
258
/* Wait until the TE bit is set*/
259
}
260
261
/* ----Stopping DMA transfer---- */
262
DMAC.CHCR1.BIT.DE = 0ul;
263 }
264
265 /*""FUNC COMMENT""*******************************************************
266 * Outline
: Initial setting of SCIF0 as an asynchronous (UART) transmit module
267 *-----------------------------------------------------------------------
268 * Include
: #include "iodefine.h"
269 *-----------------------------------------------------------------------
270 * Declaration : void io_init_scif0(int bps);
271 *-----------------------------------------------------------------------
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
: DS : DREQ select :0 Low level
: TB : cycle :0---------------
: TS : transfer size:B'00---
: IE : interrupt enable:0---
: TE : transfer end----------
: DE : DMA enable bit:0-----
December 2008
Unused
Cycle-stealing mode
Byte transfer
Disable interrupt
DMA
/* MID = SCIF0 */
/* RID = Transmission */
/* Clear AE,NMI bits
/* Enable DMA transfer on all channels
/* Enable DMA transfer
/* Disable DMA1 transfer */
SH7263/SH7203 Group
*/
*/
Page 13 of 17
*/
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