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On-chip
memory
On-chip
peripheral
module
DMA transfer
request signal
DMA transfer acknowledge signal
Interrupt controller
External ROM
External RAM
External device
(memory mapped)
External device
(with acknowledge)
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR:
DMA transfer count register
RSAR:
DMA reload source address register
SAR:
DMA source address register
RDAR:
DMA reload destination address register DEIn:
DAR:
DMA destination address register
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
Iteration
control
Register
control
Start-up
control
Request
HEIn
priority
control
DEIn
Bus
interface
Bus state
controller
CHCR:
DMAOR:
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
HEIn:
n:
Figure 1 Block Diagram of DMAC
December 2008
SH7263/SH7203 Group
DMAC module
RDMATCR_n
DMATCR_n
RSAR_n
SAR_n
RDAR_n
DAR_n
CHCR_n
DMAOR
DMARS0 to DMARS3
DMA channel control register
DMA operation register
DMA transfer half-end interrupt request to the CPU
DMA transfer end interrupt request to the CPU
0, 1, 2, 3, 4, 5, 6, 7
Page 4 of 17
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