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3. Sample Program Listing "main.c" (3)
107
/* ==== Enabling SCIF0 initialization/transfer ==== */
108
io_init_scif0(CBR_115200);
109
110
111
112
/* ==== Disabling DMA transfer ==== */
113
io_dma1_stop();
114
while(1){
115
116
}
117
}
118 /*""FUNC COMMENT""*******************************************************
119 * Outline
: Initialization for DATA transfer between memory areas with DMAC
120 *-----------------------------------------------------------------------
121 * Include
: #include "iodefine.h"
122 *-----------------------------------------------------------------------
123 * Declaration : io_init_dma1(void *src, void *dst, size_t size, int mode);
124 *-----------------------------------------------------------------------
125 * Function
:
126 *
:
127 *
:
128 *
:
129 *-----------------------------------------------------------------------
130 * Argument
: void *src
131 *
: void *dst
132 *
: size_t size
133 *
:
134 *
:
135 *
:
136 *
:
137 *
:
138 *
:
139 *
:
140 *-----------------------------------------------------------------------
141 * Return Value : void
142 *-----------------------------------------------------------------------
143 * Notice
:
144 *
: address is inconsistent.
145 *
: When interrupts are used, interrupt routines must be registered.
146 *""FUNC COMMENT END""***************************************************/
147 void io_init_dma1(void *src, void *dst, size_t size, unsigned int mode)
148 {
149
unsigned int ts;
150
unsigned long ie;
151
152
ts = mode & 0x3u;
153
ie = (mode & 0x00f0u ) >> 4u;
154
155
/* ====Setting standby control register 2(STBCR2) ==== */
156
CPG.STBCR2.BIT.MSTP8 = 0x0;
157
158
/* ---- Setting DMA channel control register ---- */
159
DMAC.CHCR1.BIT.DE = 0ul;
160
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
/* Communication mode :UART mode */
/* Bit rate :115.2Kbps */
/* TXI interrupt is generated when data in transmit FIFO is one byte */
/* Program end */
The DMAC transfers the amount of data specified by "size".
from the source address "src" to the destination address "dst."
Transfer is performed using requests from the SCIF1.
"mode" is specified for transfer size and interrupt used/not used.
:
Source address
:
Destination address
: Transfer size (byte)
unsigned int mode: Transfer mode, specifies the following with logical OR.
DMA_SIZE_BYTE
DMA_SIZE_WORD
DMA_SIZE_LONG
DMA_SIZE_LONGx4(0x0003) 16-byte transfer
DMA_INT_DISABLE(0x0000)
DMA_INT_ENABLE (0x0010) DMA transfer end interrupt disabled
Operation is not guaranteed when the alignment of the source/destination.
December 2008
(0x0000)
Byte transfer
(0x0001)
Word transfer
(0x0002)
Longword transfer
DMA transfer end interrupt disabled
/* Cancel DMAC module top mode */
/* Disable DMA transfer */
SH7263/SH7203 Group
Page 11 of 17
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