Renesas REJ06B0734-0100 Application Note page 8

2.3 Operation of Sample Program
In this sample program, SCIF transmit FIFO data empty transfer requests are made to activate DMAC channel 1, and to
transfer data from external memory to the transmit FIFO data register (SCFTDR) on SCIF channel 0. The data written
to SCFTDR on SCIF channel 0 are transmitted in UART mode. An operation timing of the sample program is shown in
figure 3.
DMA transfer using SCIF transmit FIFO data empty transfer requests
(Timing of requesting data transfer from external memory to the SCIF transmit FIFO data register: a
transfer request is made when the number of data in transmit FIFO becomes 0)
DMAC1
Bus
mastership
CPU
Internal bus
External bus
DMA transfer request
(When the DMA master
enable bit is 1)
DMA transfer count
H'29
register (DMATCR)
Transfer end flag (TE)
[Legend]
: DMA request acknowledge
REJ06B0734-0101/Rev.1.01
Data Transfer to On-chip Peripheral Modules with DMAC
One data One data
transfer transfer
Read Read
Write
Internal signal
Write to SCIF transmit FIFO data register (SCFTDR)
Write
Read Read
SCIF transmit FIFO data empty transfer request (on-chip peripheral request)
H'28
Figure 3 Operation Timing of Sample Application
December 2008
One data
transfer
Read
Write Write
Internal signal
Write Write
Read
H'27
SH7263/SH7203 Group
One data
transfer
Read
Write
Internal signal
Write
Read
H'00
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