Pinout For Swd - Segger J-Link User Manual

324
15.1.2

Pinout for SWD

The J-Link and J-Trace JTAG connector is also compatible to ARM's Serial Wire Debug (SWD).
*On later J-Link products like the J-link ULTRA, these pins are reserved for firmware exten-
sion purposes. They can be left open or connected to GND in normal debug environment.
They are not essential for JTAG/SWD in general.
The following table lists the J-Link / J-Trace SWD pinout.
PIN SIGNAL
1 VTref
Not
2
connected
3 Not used
5 Not used
7 SWDIO
9 SWCLK
11 Not used
13 SWO
15 nRESET
17 Not Used
19 5V-Supply
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should
also be connected to GND in the target system.
15.1.2.1 Target board design
We strongly advise following the recommendations given by the chip manufacturer. These
recommendations are normally in line with the recommendations given in the table Pinout
for SWD on page 324. In case of doubt you should follow the recommendations given by
the semiconductor manufacturer.
J-Link / J-Trace (UM08001)
CHAPTER 15
TYPE
This is the target reference voltage. It is used to check if the
target has power, to create the logic-level reference for the in-
Input put comparators and to control the output logic levels to the
target. It is normally fed from Vdd of the target board and
must not have a series resistor.
NC This pin is not connected in J-Link.
This pin is not used by J-Link. If the device may also be ac-
NC cessed via JTAG, this pin may be connected to nTRST, other-
wise leave open.
This pin is not used by J-Link. If the device may also be ac-
NC cessed via JTAG, this pin may be connected to TDI, otherwise
leave open.
Single bi-directional data pin. A pull-up resistor is required.
I/O
ARM recommends 100 kOhms.
Clock signal to target CPU. It is recommended that this pin is
Output pulled to a defined state on the target board. Typically con-
nected to TCK of the target CPU.
This pin is not used by J-Link. If the device may also be ac-
NC cessed via JTAG, this pin may be connected to RTCK, other-
wise leave open.
Serial Wire Output trace port. (Optional, not required for SWD
Input
communication.)
Target CPU reset signal. Typically connected to the RESET pin
I/O of the target CPU, which is typically called "nRST", "nRESET"
or "RESET". This signal is an active low signal.
NC This pin is not connected in J-Link.
This pin can be used to supply power to the target hardware.
Older J-Links may not be able to supply power on this pin. For
Output
more information about how to enable/disable the power sup-
ply, please refer to Target power supply .
Description
© 2004-2017 SEGGER Microcontroller GmbH & Co. KG
20-pin J-Link connector