4.8
I/O Memory
4.8.1
General Purpose I/O Registers
4.9
External Memory
4.10
Data Memory and Bus Arbitration
8331B–AVR–03/12
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
Up to four ports are dedicated to external memory, supporting external SRAM, SDRAM, and
memory mapped peripherals such as LCD displays. For details, refer to
Interface" on page
335. The external memory address space will always start at the end of inter-
nal SRAM.
Since the data memory is organized as four separate sets of memories, the different bus mas-
ters (CPU, DMA controller read and DMA controller write, etc.) can access different memory
sections at the same time. See
and is connected directly to internal SRAM through a pseudo-dualport (PDP) interface.
Figure 4-3.
Bus access.
DMA
CH0
CH1
CH2
CH3
Flash
EEPROM
Non-Volatile
Memory
Figure 4-3 on page
CPU
AVR core
OCD
Bus matrix
Interrupt
CRC
USB
Controller
NVM
Power
USART
Controller
Management
Event System
AC
SPI
Controller
Oscillator
ADC
TWI
Control
Timer /
DAC
I/O
Counter
Battery
Crypto
Real Time
Backup
modules
Counter
Peripherals and system modules
Atmel AVR XMEGA AU
"EBI – External Bus
24. The USB module acts as a bus master
External
Programming
PDI
SRAM
RAM
EBI
External
Memory
24
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