Page 1 AU microcontroller family. The Atmel AVR XMEGA AU is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon- trollers based on the AVR enhanced RISC architecture. The available Atmel AVR XMEGA AU modules described in this manual are: •...
Page 2: About The Manual
This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA AU microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and modules described in this manual may not be present in all Atmel AVR XMEGA AU devices.
Page 3: Overview
The AVR XMEGA AU microcontrollers is a family of low-power, high-performance, and periph- eral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel AVR XMEGA AU devices achieve throughputs approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Page 4 Atmel AVR XMEGA AU The Atmel AVR XMEGA AU devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.Block Diagram Figure 2-1. Atmel AVR XMEGA AU block diagram.
Page 5 Atmel AVR XMEGA AU Table 2-1 on page 5 a feature summary for the XMEGA AU family is shown, split into one fea- ture summary column for each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet for ordering codes and memory options.
Page 6 Atmel AVR XMEGA AU Feature Details / sub-family A3BU USB full-speed device USART Serial Communication AES-128 Crypto /CRC CRC-16 CRC-32 Chip selects – – – External Memory (EBI) SRAM SDRAM Resolution (bits) Analog to Digital 2000 2000 2000 2000 Sampling speed (kbps)
Page 7: Avr Cpu
This enables instructions to be executed on every clock cycle. For a summary of all AVR instructions, refer to ”Instruction Set Summary” on page 456. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 3-1. Block diagram of the AVR CPU architecture. 8331B–AVR–03/12...
Page 8: Alu - Arithmetic Logic Unit
Atmel AVR XMEGA AU The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation.
Page 9: Program Flow
Atmel AVR XMEGA AU 3.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: • Multiplication of unsigned integers •...
Page 10: Status Register
Atmel AVR XMEGA AU Figure 3-3 on page 10 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register.
Page 11: Register File
Atmel AVR XMEGA AU The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will auto- matically disable interrupts for up to four instructions or until the next I/O memory write.
Page 12: Ramp And Extended Indirect Registers
Atmel AVR XMEGA AU Figure 3-5. The X-, Y- and Z-registers Bit (individually) X-register Bit (X-register) Bit (individually) Y-register Bit (Y-register) Bit (individually) Z-register Bit (Z-register) The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-significant byte (MSB). In the different addressing modes, these address registers function as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
Page 13: Accessing 16-Bit Registers
Atmel AVR XMEGA AU 3.10.2 RAMPD Register This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address. Figure 3-7. The combined RAMPD + K register.
Page 14: Fuse Lock
Atmel AVR XMEGA AU the fuses and signature row. This is handled globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or execution of protected instruc- tions, are only possible after the CPU writes a signature to the CCP register. The different signatures are described in the register description.
Page 15: Register Descriptions
Atmel AVR XMEGA AU 3.14 Register Descriptions 3.14.1 CCP – Configuration Change Protection register +0x04 CCP[7:0] Read/Write Initial Value • Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of the protected instruction for a maximum period of four CPU instruc- tion cycles.
Page 16 Atmel AVR XMEGA AU +0x09 RAMPX[7:0] RAMPX Read/Write Initial Value • Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of bits required to address the available data memory is implemented for each device.
Page 17 Atmel AVR XMEGA AU ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program memory in the device is less than 128KB.
Page 18 Atmel AVR XMEGA AU 3.14.9 SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. +0x0F SREG Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for interrupts to be enabled.
Page 19: Register Summary
Atmel AVR XMEGA AU 3.15 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 Reserved – – – – – – – – +0x01 Reserved – –...
Page 20: Memories
Atmel AVR XMEGA AU 4. Memories Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage –...
Page 21: Flash Program Memory
Atmel AVR XMEGA AU A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. Flash Program Memory All XMEGA devices contain on-chip in-system reprogrammable flash memory for program stor- age.
Page 22: Fuses And Lockbits
Atmel AVR XMEGA AU application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here.
Page 23: Data Memory
Atmel AVR XMEGA AU Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory, if available. The data memory is organized as one continuous memory section, as shown in Figure 4-2 on page Figure 4-2.
Page 24: I/O Memory
Atmel AVR XMEGA AU I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory.
Page 25: Memory Timing
4.12 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 4.13 JTAG Disable It is possible to disable the JTAG interface from the application software.
Page 26: Register Description - Nvm Controller
Atmel AVR XMEGA AU 4.15 Register Description – NVM Controller – 4.15.1 ADDR0 Address register 0 The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value ADDR. This is used for addressing all NVM sections for read, write, and CRC operations.
Page 27 Atmel AVR XMEGA AU 4.15.5 DATA1 – Data register 1 +0x05 DATA[15:8] DATA1 Read/Write Initial Value • Bit 7:0 – DATA[15:8]: Data Register Byte 1 This register gives the data value byte 1 when accessing NVM locations. 4.15.6 DATA2 – Data register 2...
Page 28 Atmel AVR XMEGA AU • Bit 0 – CMDEX: Command Execute Setting this bit will execute the command in the CMD register. This bit is protected by the config- uration change protection (CCP) mechanism. Refer to ”Configuration Change Protection” on page 13 for details on the CCP.
Page 29 Atmel AVR XMEGA AU • Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level These bits enable the interrupt and select the interrupt level, as described in ”Interrupts and Pro- grammable Multilevel Interrupt Controller” on page 134. This is a level interrupt that will be triggered only when the NVMBUSY flag in the STATUS register is set to zero.
Page 30 Atmel AVR XMEGA AU 4.15.12 LOCKBITS – Lock Bit register +0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] LOCKBITS Read/Write Initial Value This register is a mapping of the NVM lock bits into the I/O memory space, which enable direct read access from the application software. Refer to ”LOCKBITS –...
Page 31: Register Descriptions - Fuses And Lock Bits
Atmel AVR XMEGA AU 4.16 Register Descriptions – Fuses and Lock bits 4.16.1 FUSEBYTE0 – Fuse Byte 0 +0x00 JTAGUID[7:0] FUSEBYTE0 Read/Write Initial Value • Bit 7 – JTAGUID[7:0]: JTAG USER ID These fuses can be used to set the default JTAG user ID for the device. During reset, the JTAGUID fuse bits will be loaded into the MCU JTAG user ID register.
Page 32 Atmel AVR XMEGA AU • Bit 6 – BOOTRST: Boot Loader Section Reset Vector This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section. The device will then start executing from the boot loader flash section after reset.
Page 33 Atmel AVR XMEGA AU • Bit: 4 – RSTDISBL: External Reset Disable This fuse can be programmed to disable the external reset pin functionality. When this is done pulling the pin low will not cause an external reset. A reset is required before this bit will be read correctly after it is changed.
Page 34 Atmel AVR XMEGA AU 4.16.5 FUSEBYTE5 – Fuse Byte 5 +0x05 – – BODACT[1:0] EESAVE BODLEVEL[2:0] FUSEBYTE5 Read/Write Initial Value – – – – – – • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to one when this register is written.
Page 35 Atmel AVR XMEGA AU 4.16.6 LOCKBITS – Lock Bit register +0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] LOCKBITS Read/Write Initial Value • Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be written to a more strict locking.
Page 36 Atmel AVR XMEGA AU Table 4-10. Boot lock bit for the application section. BLBA[1:0] Group Configuration Description No Lock - no restrictions for SPM and (E)LPM NOLOCK accessing the application section. Write lock – SPM is not allowed to write the application WLOCK section.
Page 37: Register Description - Production Signature Row
Atmel AVR XMEGA AU bits is possible by executing a chip erase command. All other access; using the TIF and OCD, is blocked if any of the Lock Bits are written to 0. These bits do not block any software access to the memory.
Page 38 Atmel AVR XMEGA AU 4.17.3 RCOSC32K – Internal 32.768kHz Oscillator Calibration register +0x02 RCOSC32K[7:0] RCOSC32K Read/Write Initial Value • Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibra- tion of the oscillator is performed during production test of the device.
Page 39 Atmel AVR XMEGA AU +0x08 LOTNUM0[7:0] LOTNUM0 Read/Write Initial Value • Bit 7:0 – LOTNUM0[7:0]: Lot Number Byte 0 This byte contains byte 0 of the lot number for the device. 4.17.7 LOTNUM1 – Lot Number register 1 +0x09 LOTNUM1[7:0]...
Page 40 Atmel AVR XMEGA AU 4.17.10 LOTNUM4 – Lot Number register 4 +0x0C LOTNUM4[7:0] LOTNUM4 Read/Write Initial Value • Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4 This byte contains byte 4 of the lot number for the device. 4.17.11 LOTNUM5 – Lot Number register 5...
Page 41 Atmel AVR XMEGA AU 4.17.14 COORDX1 – Wafer Coordinate X register 1 +0x13 COORDX1[7:0] COORDX1 Read/Write Initial Value • Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device.
Page 42 Atmel AVR XMEGA AU 4.17.18 USBCAL1 – USB Pad Calibration register 1 +0x1B USBCAL1[7:0] USBCAL1 Read/Write Initial Value • Bit 7:0 – USBCAL1[7:0]: USB Pad Calibration Register 1 This byte contains byte 1 of the USB pin calibration data, and must be loaded into the USB CALH register.
Page 43 Atmel AVR XMEGA AU • Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register. 4.17.22 ADCBCAL0 – ADCB Calibration register 0 ADCBCAL0 and ADCBCAL1 contains the calibration value for the analog to digital converter B(ADCB).
Page 44 Atmel AVR XMEGA AU 4.17.25 TEMPSENSE1 – Temperature Sensor Calibration register 1 +0x2F TEMPSENSE1[7:0] TEMPSENSE1 Read/Write Initial Value • Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1 This byte contains byte 1 of the temperature measurement. 4.17.26 DACA0OFFCAL – DACA Offset Calibration register...
Page 45 Atmel AVR XMEGA AU loaded automatically into the DAC channel 0 offset calibration register, so this must be done from software. 4.17.29 DACB0GAINCAL – DACB Gain Calibration register +0x33 DACB0GAINCAL[7:0] DACB0GAINCAL Read/Write Initial Value • Bit 7:0 – DACB0GAINCAL[7:0]: DACB0 Gain Calibration Byte This byte contains the gain calibration value for channel 0 in the digital to analog converter B (DACB).
Page 46: Register Description - General Purpose I/O Memory
Atmel AVR XMEGA AU 4.17.32 DACB1OFFCAL – DACB Offset Calibration register +0x36 DACB1OFFCAL[7:0] DACB1OFFCAL Read/Write Initial Value • Bit 7:0 – DACB1OFFCAL[7:0]: DACB1 Offset Calibration Byte This byte contains the offset calibration value for channel 1 in the digital to analog converter B (DACB).
Page 47: Register Descriptions - Mcu Control
Atmel AVR XMEGA AU 4.20 Register Descriptions – MCU Control 4.20.1 DEVID0 – Device ID register 0 DEVID0, DEVID1 and DEVID2 contain the byte identification that identifies each microcontroller device type. For details on the actual ID, refer to the device datasheet.
Page 48 Atmel AVR XMEGA AU • Bit 3:0 – REVID[3:0]: Revision ID These bits contains the device revision. 0 = A, 1= B and so on. 4.20.5 JTAGUID – JTAG User ID register +0x04 JTAGUID[7:0] JTAGUID Read/Write Initial Value • Bit 7:0 – JTAGUID[7:0]: JTAG User ID The JTAGUID can be used to identify two devices with identical device ID in a JTAG scan chain.
Page 49 Atmel AVR XMEGA AU ule is enabled. This reduces the peak current consumption during startup of the module. For maximum effect the start-up delay should be set so that it is larger than 0.5µs. Table 4-13. Analog startup delay. STARTUPDLYx...
Page 50 Atmel AVR XMEGA AU • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 2 – AWEXELOCK: Advanced Waveform Extension Lock for TCE0 Setting this bit will lock all registers in the AWEXE module for timer/counter E0 for further modifi- cation.
Page 51: Register Summary - Nvm Controller
Atmel AVR XMEGA AU 4.21 Register Summary - NVM Controller Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 ADDR0 Address Byte 0 +0x01 ADDR1 Address Byte 1 +0x02...
Page 52: Register Summary - Production Signature Row
Atmel AVR XMEGA AU 4.23 Register Summary - Production Signature Row Address Auto Load Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 RCOSC2M RCOSC2M[7:0] +0x01 RCOSC2MA RCOSC2MA[7:0] +0x02 RCOSC32K...
Page 53: Register Summary - General Purpose I/O Registers
Atmel AVR XMEGA AU 4.24 Register Summary – General Purpose I/O Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 GPIOR0 GPIOR[7:0] +0x01 GPIOR1 GPIOR[7:0] +0x02 GPIOR2 GPIOR[7:0]...
Page 54: Dmac - Direct Memory Access Controller
Atmel AVR XMEGA AU 5. DMAC - Direct Memory Access Controller Features • Allows high speed data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory –...
Page 55: Dma Transaction
Atmel AVR XMEGA AU Figure 5-1. DMA Overview. DMA Channel 0 DMA trigger / CTRLA Event CTRLB TRIGSRC Enable Arbitration Burst Control Logic R/W Master port Arbiter TRFCNT DESTADDR Read REPCNT SRCADDR Write DMA Channel 1 matrix DMA Channel 2...
Page 56: Transfer Triggers
Atmel AVR XMEGA AU Figure 5-2. DMA transaction. Four-byte burst mode Block size: 12 bytes Repeat count: 2 Burst transfer Block transfer DMA transaction Transfer Triggers DMA transfers can be started only when a DMA transfer request is detected. A transfer request can be triggered from software, from an external trigger source (peripheral), or from an event.
Page 57: Double Buffering
Atmel AVR XMEGA AU one or more channels should have a fixed priority or if a round robin scheme should be used. A round robin scheme means that the channel that last transferred data will have the lowest priority. Double Buffering To allow for continuous transfer, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.
Page 58: Interrupts
Atmel AVR XMEGA AU 5.12 Interrupts The DMA controller can generate interrupts when an error is detected on a DMA channel or when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt vector, and there are different interrupt flags for error and transaction complete.
Page 59: Register Description - Dma Controller
Atmel AVR XMEGA AU 5.13 Register Description – DMA Controller 5.13.1 CTRL – Control register +0x00 ENABLE RESET – – DBUFMODE[1:0] PRIMODE[1:0] CTRL Read/Write Initial Value • Bit 7 – ENABLE: Enable Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty, and the DMA data transfer is aborted.
Page 60 Atmel AVR XMEGA AU 5.13.2 INTFLAGS – Interrupt Status register +0x03 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF INTFLAGS Read/Write Initial Value • Bit 7:4 – CHnERRIF[3:0]: Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location will clear the flag.
Page 61: Register Description - Dma Channel
Atmel AVR XMEGA AU 5.13.5 TEMPH – Temporary Register High +0x07 TEMP[15:8] TEMPH Read/Write Initial Value • Bit 7:0 – TEMP[15:8]: Temporary Register This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is stored when it is written by the CPU.
Page 62 Atmel AVR XMEGA AU • Bit 2 – SINGLE: Single-Shot Data transfer Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled.
Page 63 Atmel AVR XMEGA AU 5.14.2 CTRLB – Control register B +0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] CTRLB Read/Write Initial Value • Bit 7 – CHBUSY: Channel Busy When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag is automatically cleared when the DMA channel is disabled, when the channel transaction complete interrupt flag is set or when the channel error interrupt flag is set.
Page 64 Atmel AVR XMEGA AU • Bit 7:6 – SRCRELOAD[1:0]: Channel Source Address Reload These bits decide the DMA channel source address reload according to Table 5-5. A write to these bits is ignored while the channel is busy. Table 5-5.
Page 65 Atmel AVR XMEGA AU Table 5-8. DMA channel destination address mode settings. DESTDIR[1:0] Group Configuration Description FIXED Fixed Increment Decrement Reserved 5.14.4 TRIGSRC – Trigger Source +0x03 TRIGSRC[7:0] TRIGSRC Read/Write Initial Value • Bit 7:0 – TRIGSRC[7:0]: Channel Trigger Source Select These bits select which trigger source is used for triggering a transfer on the DMA channel.
Page 66 Atmel AVR XMEGA AU Table 5-9. DMA trigger source base values for all modules and peripherals. (Continued) TRIGSRC Base Value Group Configuration Description 0x4A SPIC SPI C DMA triggers value 0x4B USARTC0 USART C0 DMA triggers base value 0x4E USARTC1...
Page 67 Atmel AVR XMEGA AU Table 5-12. DMA trigger source offset values for timer/ counter triggers. TRGSRC Offset Value Group Configuration Description +0x00 Overflow/underflow +0x01 Error +0x02 Compare or capture channel A +0x03 Compare or capture channel B +0x04 Compare or capture channel C...
Page 68 Atmel AVR XMEGA AU • Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count register High These bits hold the MSB of the 16-bit block transfer count. The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig- ger, DMA will be doing 0xFFFF transfers.
Page 69 Atmel AVR XMEGA AU 5.14.10 SRCADDR2 – Channel Source Address 2 Reading and writing 24-bit values require special attention. For details, refer to ”Accessing 24- and 32-bit Registers” on page +0x0A SRCADDR[23:16] SRCADDR2 Read/Write Initial Value • Bit 7:0 – SRCADDR[23:16]: Channel Source Address 2 These bits hold byte 2 of the 24-bit source address.
Page 70: Register Summary - Dma Controller
Atmel AVR XMEGA AU 5.15 Register Summary – DMA Controller Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL ENABLE RESET DBUFMODE[1:0] PRIMODE[1:0] +0x01 Reserved – – –...
Page 71: Event System
Atmel AVR XMEGA AU 6. Event System Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed response time •...
Page 72: Events
Atmel AVR XMEGA AU Figure 6-1. Event system overview and connected peripherals. CPU / Software Controller Event Routing Network Prescaler Real Time Event Counter System Controller Timer / Counters Port pins IRCOM The event routing network consists of eight software-configurable multiplexers that control how events are routed and used.
Page 73 Atmel AVR XMEGA AU Figure 6-2. Example of event source, generator, user, and action. Event Generator Event User Timer/Counter Compare Match Channel Sweep Event Routing Over-/Underflow Single Network Conversion Error Event Action Selection Event Source Event Action Events can also be generated manually in software.
Page 74: Event Routing Network
Atmel AVR XMEGA AU Software-generated events last for one clock cycle and will overwrite events from other event generators on that event channel during that clock cycle. Table 6-1 on page 74 shows the different events, how they can be manually generated, and how they are decoded.
Page 75 Atmel AVR XMEGA AU Figure 6-3. Event routing network. Event Channel 7 Event Channel 6 Event Channel 5 Event Channel 4 Event Channel 3 Event Channel 2 Event Channel 1 Event Channel 0 (10) TCC0 TCC1 CH0CTRL[7:0] CH0MUX[7:0] (10) TCD0...
Page 76: Event Timing
Atmel AVR XMEGA AU Event Timing An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise stated, an event lasts for one peripheral clock cycle.
Page 77 Atmel AVR XMEGA AU Figure 6-4. Quadrature signals from a rotary encoder. 1 cycle / 4 states Forward Direction QDPH0 QDPH90 QDINDX Backward Direction QDPH0 QDPH90 QDINDX Figure 6-4 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the two quadrature signals.
Page 78: Register Description
Atmel AVR XMEGA AU • Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder. • Enable the timer/counter without clock prescaling. The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the timer/counter count register.
Page 79 Atmel AVR XMEGA AU Table 6-3. CHnMUX[7:0] bit settings. CHnMUX[7:4] CHnMUX[3:0] Group Configuration Event Source 0001 ACB_CH1 ACB channel 1 0001 ACB_WIN ACB window 0001 (Reserved) 0001 (Reserved) 0010 ADCA_CHn ADCA channel n (n =0, 1, 2 or 3) 0010...
Page 80 Atmel AVR XMEGA AU Table 6-4. Timer/counter events. (Continued) T/C Event E Group Configuration Event Type TCxn_CCB Capture or compare B (x = C, D, E or F) (n= 0 or 1) TCxn_CCC Capture or compare C (x = C, D, E or F) (n= 0)
Page 81 Atmel AVR XMEGA AU Table 6-6. Digital filter coefficient values . DIGFILT[2:0] Group Configuration Description 1SAMPLE One sample 2SAMPLES Two samples 3SAMPLES Three samples 4SAMPLES Four samples 5SAMPLES Five samples 6SAMPLES Six samples 7SAMPLES Seven samples 8SAMPLES Eight samples 6.8.3 STROBE –...
Page 82: Register Summary
Atmel AVR XMEGA AU Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CH0MUX CH0MUX[7:0] +0x01 CH1MUX CH1MUX[7:0] +0x02 CH2MUX CH2MUX[7:0] +0x03 CH3MUX CH3MUX[7:0] +0x04 CH4MUX CH4MUX[7:0]...
Page 83: System Clock And Clock Options
Atmel AVR XMEGA AU 7. System Clock and Clock Options Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output •...
Page 84 Atmel AVR XMEGA AU Figure 7-1. The clock system, clock sources, and clock distribution. Real Time Non-Volatile Peripherals AVR CPU Counter Memory PER2 PER4 System Clock Prescalers Brown-out Watchdog Prescaler Detector Timer System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC PLLSRC XOSCSEL 32 kHz 32.768 kHz...
Page 85: Clock Distribution
Atmel AVR XMEGA AU Clock Distribution Figure 7-1 on page 84 presents the principal clock distribution system used in XMEGA devices. 7.3.1 System Clock - Clk The system clock is the output from the main system clock selection. This is fed into the prescal- ers that are used to generate all internal clocks except the asynchronous and USB clocks.
Page 86 Atmel AVR XMEGA AU 7.4.1.2 32.768kHz Calibrated Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output.
Page 87: System Clock Selection And Prescalers
Atmel AVR XMEGA AU Figure 7-3. External clock drive configuration. General Purpose XTAL2 External Clock XTAL1 Signal 7.4.2.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in...
Page 88: Pll With 1X-31X Multiplication Factor
Atmel AVR XMEGA AU Figure 7-5. System clock selection and prescalers. Clock Selection Internal 32.768kHz Osc. PER4 PER2 Internal 2MHz Osc. Internal 32MHz Osc. Prescaler A Prescaler B Prescaler C 1, 2, 4, ... , 512 1, 2, 4 1, 2 Internal PLL.
Page 89: Dfll 2Mhz And Dfll 32Mhz
Atmel AVR XMEGA AU DFLL 2MHz and DFLL 32MHz Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to do automatic run-time calibration of the oscillator and compensate for temperature and voltage drift.
Page 90: Pll And External Clock Source Failure Monitor
Atmel AVR XMEGA AU The value that should be written to the COMP register is given by the following formula: COMP = RCnCREF When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to adjust the oscillator frequency.
Page 91 Atmel AVR XMEGA AU • Issue a non-maskable interrupt (NMI) If the PLL or external clock source fails when not being used for the system clock, it is automati- cally disabled, and the system clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources above 32kHz.
Page 92: Register Description - Clock
Atmel AVR XMEGA AU Register Description – Clock 7.9.1 CTRL – Control register +0x00 – – – – – SCLKSEL[2:0] CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 93 Atmel AVR XMEGA AU • Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits can be written at run-time to change the frequency of the Clk...
Page 94 Atmel AVR XMEGA AU 7.9.3 LOCK – Lock register +0x02 – – – – – – – LOCK LOCK Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 95 Atmel AVR XMEGA AU • Bit 0 – RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected RTC clock source for the real-time counter. 7.9.5 USBSCTRL – USB Control register +0x04 – – USBPSDIV[2:0] USBSRC[1:0] USBSEN USBSCTRL...
Page 96: Register Description - Oscillator
Atmel AVR XMEGA AU 7.10 Register Description – Oscillator 7.10.1 CTRL – Oscillator Control register +0x00 – – – PLLEN XOSCEN RC32KEN RC32MEN RC2MEN CTRL Read/Write Initial Value • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 97 Atmel AVR XMEGA AU 7.10.2 STATUS – Oscillator Status register +0x01 – – – PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY STATUS Read/Write Initial Value • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 98 Atmel AVR XMEGA AU Table 7-7. 16MHz crystal oscillator frequency range selection. Typical Frequency Recommended Range for FRQRANGE[1:0] Group Configuration Range Capacitors C1 and C2 (pF) 04TO2 0.4MHz - 2MHz 100-300 2TO9 2MHz - 9MHz 10-40 9TO12 9MHz - 12MHz...
Page 99 Atmel AVR XMEGA AU 7.10.4 XOSCFAIL – XOSC Failure Detection register +0x03 – – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN XOSCFAIL Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 100 Atmel AVR XMEGA AU 7.10.6 PLLCTRL – PLL Control register +0x05 PLLSRC[1:0] PLLDIV PLLFAC[4:0] PLLCTRL Read/Write Initial Value • Bit 7:6 – PLLSRC[1:0]: Clock Source The PLLSRC bits select the input source for the PLL according to Table 7-9 on page 100.
Page 101: Register Description - Dfll32M/Dfll2M
Atmel AVR XMEGA AU Table 7-10. 32MHz oscillator reference selection. RC32MCREF[1:0] Group Configuration Description RC32K 32.768kHz internal oscillator XOSC32 32.768kHz crystal oscillator on TOSC USBSOF USB start of frame — Reserved • Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference This bit is used to select the calibration source for the 2MHz DFLL.
Page 102 Atmel AVR XMEGA AU • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6:0 – CALA[6:0]: DFLL Calibration Bits These bits hold the part of the oscillator calibration value that is used for automatic runtime cali- bration.
Page 103 Atmel AVR XMEGA AU 7.11.5 COMP2 – DFLL Compare register Byte 2 +0x06 COMP[15:8] COMP2 Read/Write Initial Value • Bit 7:0 – COMP2[15:8]: Compare Register Byte 2 These bits hold byte 2 of the 16-bit compare register. Table 7-11. Nominal DFLL32M COMP values for different output frequencies.
Page 104: Register Summary - Clock
Atmel AVR XMEGA AU 7.12 Register Summary - Clock Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – SCLKSEL[2:0] +0x01 PSCTRL – PSADIV[4:0]...
Page 105: Power Management And Sleep Modes
Atmel AVR XMEGA AU 8. Power Management and Sleep Modes Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable clock and turn off unused peripherals in active and idle...
Page 106 Atmel AVR XMEGA AU Table 8-1 on page 106 shows the different sleep modes and the active clock domains, oscilla- tors, and wake-up sources. Table 8-1. Active clock domains and wake-up sources in the different sleep modes. Active Clock Domain...
Page 107: Power Reduction Registers
Atmel AVR XMEGA AU 8.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
Page 108 Atmel AVR XMEGA AU 8.5.4 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and, hence, always consume power.
Page 109: Register Description - Sleep
Atmel AVR XMEGA AU Register Description – Sleep 8.6.1 CTRL – Control register +0x00 – – – – SMODE[2:0] CTRL Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 110 Atmel AVR XMEGA AU • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6 – USB: USB Module Setting this bit stops the clock to the USB module.
Page 111 Atmel AVR XMEGA AU • Bit 1 – ADC: Power Reduction ADC Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped. • Bit 0 – AC: Power Reduction Analog Comparator Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown.
Page 112: Register Summary - Sleep
Atmel AVR XMEGA AU Register Summary – Sleep Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – SMODE[2:0] Register Summary – Power Reduction Address...
Page 113: Reset System
Atmel AVR XMEGA AU 9. Reset System Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset –...
Page 114: Reset Sequence
Atmel AVR XMEGA AU Figure 9-1. Reset system overview. MCU Status Register (MCUSR) Power-on Reset Brown-out BODLEVEL [2:0] Reset Pull-up Resistor External SPIKE Reset FILTER Reset Software Reset Watchdog Reset Delay Counters Oscillator TIMEOUT SUT[1:0] Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active.
Page 115: Reset Sources
Atmel AVR XMEGA AU Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for Clk 9.3.2 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from the calibration row to the calibration registers.
Page 116 Atmel AVR XMEGA AU When the BOD is enabled and V decreases to a value below the trigger level (V Figure BOT- 9-4), the brownout reset is immediately activated. When V increases above the trigger level (V Figure 9-4), the reset counter starts the...
Page 117 Atmel AVR XMEGA AU • Enabled: In this mode, the V level is continuously monitored, and a drop in V below V for a period of t will give a brownout reset • Sampled: In this mode, the BOD circuit will sample the V level with a period identical to that of the 1kHz output from the ultra low power (ULP) internal oscillator.
Page 118 Atmel AVR XMEGA AU Figure 9-6. Watchdog reset. Cycles 1-2 2MHz For information on configuration and use of the WDT, refer to the ”WDT – Watchdog Timer” on page 128. 9.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the soft- ware reset bit in the reset control register.The reset will be issued within two CPU clock cycles...
Page 119: Register Description
Atmel AVR XMEGA AU Register Description 9.5.1 STATUS – Status register +0x00 – – PDIRF WDRF BORF EXTRF PORF STATUS Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 120: Register Summary
Atmel AVR XMEGA AU Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 STATUS – – PDIRF WDRF BORF EXTRF PORF +0x01 CTRL – – – –...
Page 121: Battery Backup System
Atmel AVR XMEGA AU 10. Battery Backup System 10.1 Features • Integrated battery backup system ensuring continuos, real-time clock during main power failure • Battery backup power supply from dedicated V pin to power: – One 32-bit real-time counter – One ultra low power 32.768kHz crystal oscillator with failure detection monitor –...
Page 122: Battery Backup System
Atmel AVR XMEGA AU 10.3 Battery Backup System The battery backup system consists of a V power supervisor, a power switch, a crystal oscil- lator with failure monitor, a 32-bit real-time counter (RTC), and two backup registers. Figure 10-1. Battery backup system and its power domain implementation.
Page 123: Configuration
Atmel AVR XMEGA AU 10.3.3 Crystal Oscillator with Failure Monitor The crystal oscillator (XOSC) supports connection of a external 32.768kHz crystal. It provides a prescaled clock output selectable to 1.024kHz or 1Hz. The crystal oscillator is designed for ultra low power consumption and by default is configured for low ESR and load capacitance crystals.
Page 124 Atmel AVR XMEGA AU 10.5.2 Main Power Restore and Start-up Sequence At every startup after main power is restored, the software should: 1. Control the main reset source to determine that a POR or BOD took place. 2. Check for power on the V pin by reading the BBPWR flag.
Page 125: Register Description
Atmel AVR XMEGA AU 10.6 Register Description 10.6.1 CTRL: Control register +0x00 – – HIGHESR XOSCSEL XOSCEN XOSCFDEN ACCEN RESET CTRL Read/Write initial Value • Bit 7: 6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Page 126 Atmel AVR XMEGA AU This bit is protected by the Configuration Change Protection mechanism. For a detailed descrip- tion, refer to ”Configuration Change Protection” on page 10.6.2 STATUS: Status register +0x01 BBPWR – – – XOSCRDY XOSCFAIL BBBODF BBPODF STATUS...
Page 127: Register Summary
Atmel AVR XMEGA AU • Bit 7:0 – BACKUP0[7:0]: Backup Register 0 This register can be used to store data in the battery backup system before the main power is lost or removed. 10.6.4 BACKUP1: Battery Backup register 1 +0x03...
Page 128: Wdt - Watchdog Timer
Atmel AVR XMEGA AU 11. WDT – Watchdog Timer 11.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator •...
Page 129: Window Mode Operation
Atmel AVR XMEGA AU Figure 11-1. Normal mode operation. 11.4 Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window time- out period (TO ) and the normal timeout period (TO ). The closed window timeout period WDTW defines a duration of from 8ms to 8s where the WDT cannot be reset.
Page 130: Configuration Protection And Lock
Atmel AVR XMEGA AU 11.6 Configuration Protection and Lock The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings. The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s change enable bit must be written at the same time.
Page 131 Atmel AVR XMEGA AU Table 11-1. Watchdog timeout periods (Continued). PER[3:0] Group Configuration Typical Timeout Periods 0110 512CLK 0.512s 0111 1KCLK 1.0s 1000 2KCLK 2.0s 1001 4KCLK 4.0s 1010 8KCLK 8.0s 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111...
Page 132 Atmel AVR XMEGA AU The initial values of these bits are set by the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are not in use. In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by the configuration change protection mechanism.
Page 133: Register Summary
Atmel AVR XMEGA AU 11.7.3 STATUS – Status register +0x02 – – – – – – – SYNCBUSY STATUS Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 134: Interrupts And Programmable Multilevel Interrupt Controller
Atmel AVR XMEGA AU 12. Interrupts and Programmable Multilevel Interrupt Controller 12.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address –...
Page 135: Interrupts
Atmel AVR XMEGA AU request. The RET (subroutine return) instruction cannot be used when returning from the inter- rupt handler routine, as this will not return the PMIC to its correct state. Figure 12-1. Interrupt controller overview Interrupt Controller Priority...
Page 136 Atmel AVR XMEGA AU 12.4.1 NMI – Non-Maskable Interrupts Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non- maskable interrupts must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
Page 137 Atmel AVR XMEGA AU Figure 12-2. Interrupt execution of a multicycle instruction. If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
Page 138: Interrupt Level
Atmel AVR XMEGA AU 12.5 Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre- sponding bit values for the interrupt level configuration of all interrupts is shown in Table 12-1.
Page 139 Atmel AVR XMEGA AU Figure 12-3. Static priority. Lowes t Addres s IVEC 0 Highes t Priority IVEC x IVEC x+1 Highes t Addres s IVEC N Lowes t Priority 12.6.2 Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts.
Page 140: Interrupt Vector Locations
Atmel AVR XMEGA AU 12.7 Interrupt vector locations Table 12-2 on page 140 shows reset and Interrupt vectors placement for the various combina- tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
Page 141: Register Description
Atmel AVR XMEGA AU 12.8 Register Description 12.8.1 STATUS – Status register +0x00 NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX STATUS Read/Write Initial Value • Bit 7 – NMIEX: Non-Maskable Interrupt Executing This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the interrupt handler.
Page 142: Register Summary
Atmel AVR XMEGA AU 12.8.3 CTRL – Control register +0x02 RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN CTRL Read/Write Initial Value • Bit 7 – RREN: Round-robin Scheduling Enable When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts.
Page 143: O Ports
Atmel AVR XMEGA AU 13. I/O Ports 13.1 Features • General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O •...
Page 144: I/O Pin Use And Configuration
Atmel AVR XMEGA AU Figure 13-1 on page 144 shows the I/O pin functionality and the registers that are available for controlling a pin. Figure 13-1. General I/O pin functionality. Pull Enable Pull Keep PINnCTRL Pull Direction Input Disable Wired AND/OR...
Page 145 Atmel AVR XMEGA AU The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin.
Page 146 Atmel AVR XMEGA AU 13.3.1.2 Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull- up when set as input. Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input).
Page 147: Reading The Pin Value
Atmel AVR XMEGA AU Figure 13-6. Output configuration - Wired-OR with optional pull-down. OUTn 13.3.4 Wired-AND In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are written to zero. When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal or an external pull-resistor.
Page 148: Input Sense Configuration
Atmel AVR XMEGA AU Figure 13-8. Synchronization when reading a pin value. PERIPHERAL CLK INSTRUCTIONS lds r17, PORTx+IN SYNCHRONIZER FLIPFLOP 0x00 0xFF pd, max pd, min 13.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level.
Page 149: Port Interrupt
Atmel AVR XMEGA AU 13.6 Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts must be enabled before they can be used. Which sense configurations can be used to generate interrupts is dependent on whether synchronous or asynchronous input sensing is available for the selected pin.
Page 150: Port Event
Atmel AVR XMEGA AU Table 13-3. Limited asynchronous sense support. Sense Settings Supported Interrupt Description Rising edge Falling edge Any edge Pin value must be kept unchanged during wake up Low level Pin level must be kept unchanged during wake up 13.7...
Page 151: Slew Rate Control
Atmel AVR XMEGA AU Figure 13-10. Port override signals and related logic. Pull Enable Pull Keep Pull Direction PINnCTRL Digital Input Disable (DID) DID Override Value DID Override Enable Wired AND/OR Slew Rate Limit Inverted I/O OUTn OUT Override Value...
Page 152: Multi-Pin Configuration
Atmel AVR XMEGA AU 13.11 Multi-pin configuration The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written, while avoiding several pins being written the same way during identical write operations.
Page 153: Register Descriptions - Ports
Atmel AVR XMEGA AU 13.13 Register Descriptions – Ports 13.13.1 DIR – Data Direction register +0x00 DIR[7:0] Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured as an output pin.
Page 154 Atmel AVR XMEGA AU • Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
Page 155 Atmel AVR XMEGA AU 13.13.8 OUTTGL – Data Output Value Toggle register +0x07 OUTTGL[7:0] OUTTGL Read/Write Initial Value • Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins.
Page 156 Atmel AVR XMEGA AU • Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense config- uration for each pin is decided by the PINnCTRL registers.
Page 157 Atmel AVR XMEGA AU • Bit 4 – USART0: USART0 Remap Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4]. • Bit 3 – TC0D: Timer/Counter 0 Output Compare D Setting this bit will move the location of OC0D from Px3 to Px7.
Page 158 Atmel AVR XMEGA AU Table 13-5. Output/pull configuration. Description OPC[2:0] Group Configuration Output Configuration Pull Configuration TOTEM Totem-pole (N/A) BUSKEEPER Totem-pole Bus-keeper PULLDOWN Totem-pole Pull-down (on input) PULLUP Totem-pole Pull-up (on input) WIREDOR Wired-OR (N/A) WIREDAND Wired-AND (N/A) WIREDORPULL Wired-OR...
Page 159: Register Descriptions - Port Configuration
Atmel AVR XMEGA AU 13.14 Register Descriptions – Port Configuration 13.14.1 MPCMASK – Multi-pin Configuration Mask register +0x00 MPCMASK[7:0] MPCMASK Read/Write Initial Value • Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n makes pin n part of the multi-pin configuration.
Page 160 Atmel AVR XMEGA AU • Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the actual port registers.
Page 161 Atmel AVR XMEGA AU Table 13-8 on page 161 shows the possible configurations. Table 13-8. Event output pin selection. EVOUT[1:0] Group Configuration Description Event output disabled Event channel 0 output on PORTC Event channel 0 output on PORTD Event channel 0 output on PORTE •...
Page 162 Atmel AVR XMEGA AU • Bit 3:2 – EBIADROUT[1:0]: EBI Address Output The maximum configuration of the external bus interface (EBI) requires up to 32 dedicated pins. For devices with only 24 EBI pins available, eight additional pins can be enabled and placed on alternate pin locations in order to get a full 32-pin EBI.
Page 163 Atmel AVR XMEGA AU Table 13-14. Event channel output selection. EVOUTSEL[2:0] Group Configuration Description Event channel 0 output to pin Event channel 1 output to pin Event channel 2 output to pin Event channel 3 output to pin Event channel 4 output to pin...
Page 164: Register Descriptions - Virtual Port
Atmel AVR XMEGA AU 13.15 Register Descriptions – Virtual Port 13.15.1 DIR – Data Direction +0x00 DIR[7:0] Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by VPCTRLA, vir- tual port-map control register A or VPCTRLB, virtual port-map control register B.
Page 165 Atmel AVR XMEGA AU 13.15.4 INTFLAGS – Interrupt Flag register +0x03 – – – – – – INT1IF INT0IF INTFLAGS Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 166: Register Summary - Ports
Atmel AVR XMEGA AU 13.16 Register Summary – Ports Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 DIR[7:0] +0x01 DIRSET DIRSET[7:0] +0x02 DIRCLR DIRCLR[7:0] +0x03 DIRTGL DIRTGL[7:0] +0x04...
Page 167: Interrupt Vector Summary - Ports
Atmel AVR XMEGA AU 13.19 Interrupt Vector Summary – Ports Table 13-15. Port interrupt vectors and their word offset address. Offset Source Interrupt Description 0x00 INT0_vect Port interrupt vector 0 offset 0x02 INT1_vect Port interrupt vector 1 offset 8331B–AVR–03/12...
Page 168: Tc0/1 - 16-Bit Timer/Counter Type 0 And 1
14.2 Overview Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input cap- ture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
Page 169 Atmel AVR XMEGA AU There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each.
Page 170: Block Diagram
Atmel AVR XMEGA AU “compare channels.” When used for capture operations, the CC channels are referred to as “capture channels.” 14.3 Block Diagram Figure 14-2 on page 170 shows a detailed block diagram of the timer/counter without the extensions. Figure 14-2. Timer/counter block diagram.
Page 171: Clock And Event Sources
Atmel AVR XMEGA AU A prescaled peripheral clock and events from the event system can be used to control the coun- ter. The event system is also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system (QDEC), the timer/counter can be used for quadrature decoding.
Page 172: Counter Operation
Atmel AVR XMEGA AU Figure 14-4. Period and compare double buffering. "data write" "write enable" CCxBUF UPDATE "match" When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case the buffer valid flag is set on the capture event, as shown in Figure 14-5.
Page 173 Atmel AVR XMEGA AU Figure 14-6. Normal operation. CNT written "update" BOTTOM As shown in Figure 14-6, it is possible to change the counter value when the counter is running. The write access has higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed during normal operation.
Page 174 Atmel AVR XMEGA AU Figure 14-7. Changing the period without buffering. Counter Wraparound "update" "write" BOTTOM New TOP written to New TOP written to PER that is higher PER that is lower than current CNT than current CNT A counter wraparound can occur in any mode of operation when up-counting without buffering,...
Page 175: Capture Channel
Atmel AVR XMEGA AU 14.7 Capture Channel The CC channels can be used as capture channels to capture external events and give them a timestamp. To use capture, the counter must be set for normal operation. Events are used to trigger the capture; i.e., any events from the event system, including pin change from any pin, can trigger a capture operation.
Page 176 Atmel AVR XMEGA AU Figure 14-11. Input capture timing. events BOTTOM Capture 0 Capture 1 Capture 2 Capture 3 14.7.2 Frequency Capture Selecting the frequency capture event action makes the enabled capture channel perform an input capture and restart on positive edge events. This enables the timer/counter to measure the period or frequency of a signal directly.
Page 177: Compare Channel
Atmel AVR XMEGA AU 14.7.3 Pulse Width Capture Selecting the pulse width measure event action makes the enabled compare channel perform the input capture action on falling edge events and the restart action on rising edge events. The counter will then restart on positive edge events, and the input capture will be performed on the negative edge event.
Page 178 Atmel AVR XMEGA AU synchronization prevents the occurrence of odd-length, non-symmetrical pulses for glitch-free output. 14.8.1 Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following requirements must be fulfilled: 1.
Page 179 Atmel AVR XMEGA AU to TOP and then restarts from BOTTOM. The waveform generator (WG) output is set on the compare match between the CNT and CCx registers and cleared at TOP. Figure 14-15. Single-slope pulse width modulation. "update" Period (T)
Page 180 Atmel AVR XMEGA AU Figure 14-16. Dual-slope pulse width modulation. "update" Period (T) CCx=BOTTOM CCx=TOP "match" BOTTOM WG Output Using dual-slope PWM results in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX).
Page 181: Interrupts And Events
Atmel AVR XMEGA AU Figure 14-17. Port override for timer/counter 0 and 1. Waveform CCExEN INVEN 14.9 Interrupts and events The timer/counter can generate both interrupts and events. The counter can generate an inter- rupt on overflow/underflow, and each CC channel has a separate interrupt that is used for compare or capture.
Page 182: Register Description
Atmel AVR XMEGA AU 14.12 Register Description 14.12.1 CTRLA – Control register A +0x00 – – – – CLKSEL[3:0] CTRLA Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 183 Atmel AVR XMEGA AU • Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode...
Page 184 Atmel AVR XMEGA AU 14.12.4 CTRLD – Control register D +0x03 EVACT[2:0] EVDLY EVSEL[3:0] CTRLD Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to...
Page 185 Atmel AVR XMEGA AU Table 14-6. Timer event source selection. EVSEL[3:0] Group Configuration Event Source 0000 None 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1nnn Event channel n, n={0,...,7} 14.12.5 CTRLE – Control register E +0x04 –...
Page 186 Atmel AVR XMEGA AU • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the timer error interrupt and select the interrupt level as described in ”Inter-...
Page 187 Atmel AVR XMEGA AU • Bit 3:2 – CMD[1:0]: Command These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero. Table 14-8. Command selections Group Configuration...
Page 188 Atmel AVR XMEGA AU 14.12.10 INTFLAGS – Interrupt Flag register +0x0C CCDIF CCCIF CCBIF CCAIF – – ERRIF OVFIF INTFLAGS Read/Write Initial Value • Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the corresponding CC channel.
Page 189 Atmel AVR XMEGA AU For more details, refer to ”Accessing 16-bit Registers” on page +0x0F TEMP[7:0] TEMP Read/Write Initial Value 14.12.12 CNTL – Counter register L The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the timer/counter.
Page 190 Atmel AVR XMEGA AU 14.12.15 PERH – Period register H +0x27 PER[15:8] PERH Read/Write Initial Value • Bit 7:0 – PER[15:8] These bits hold the MSB of the 16-bit period register. 14.12.16 CCxL – Compare or Capture x register L The CCxH and CCxL register pair represents the 16-bit value, CCx.
Page 191 Atmel AVR XMEGA AU • Bit 7:0 – PERBUF[7:0] These bits hold the LSB of the 16-bit period buffer register. 14.12.19 PERBUFH – Timer/Counter Period Buffer H +0x37 PERBUF[15:8] PERBUFH Read/Write Initial Value • Bit 7:0 – PERBUF[15:8] These bits hold the MSB of the 16-bit period buffer register.
Page 192: Register Summary
Atmel AVR XMEGA AU 14.13 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRLA – – – – CLKSEL[3:0] +0x01 CTRLB CCDEN CCCEN CCBEN CCAEN WGMODE[2:0]...
Page 193: Tc2 - 16-Bit Timer/Counter Type 2
Atmel AVR XMEGA AU 15. TC2 – 16-bit Timer/Counter Type 2 15.1 Features • A system of two eight-bit timer/counters – Low-byte timer/counter – High-byte timer/counter • Eight compare channels – Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte timer/counter •...
Page 194: Clock Sources
Atmel AVR XMEGA AU 15.3 Block Diagram Figure 15-1. Block diagram of the 16-bit timer/counter 0 with split mode. Base Counter Clock Select HPER LPER CTRLA "count high" Counter "load high" HUNF "count low" (INT/DMA Req.) Control Logic HCNT LCNT "load low"...
Page 195: Counter Operation
Atmel AVR XMEGA AU Figure 15-2. Clock selection. Common Event events {0,...,15} Prescaler System event channels {1,2,4,8,64,256,1024} CLKSEL The peripheral clock (clk ) is fed into the common prescaler (common for all timer/counters in a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the whole range of time prescalings from 1 to 2 is available through the event system.
Page 196: Compare Channel
Atmel AVR XMEGA AU Figure 15-4. Changing the period. "reload" "write" BOTTOM New TOP written to New TOP written to PER that is higher PER that is lower than current CNT than current CNT 15.6 Compare Channel Each compare channel continuously compares the counter value with the CMPx register. If CNT equals CMPx, the comparator signals a match.
Page 197: Interrupts And Events
Atmel AVR XMEGA AU The PER register defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the maximum resolution is eight bits (PER=MAX). The following equation is used to calculate the exact resolution for a single-slope PWM...
Page 198: Dma Support
Atmel AVR XMEGA AU 15.8 DMA Support Timer/counter underflow and compare interrupt flags can trigger a DMA transaction. The acknowledge condition that clears the flag/request is listed in Table 15-1 on page 198. Table 15-1. DMA request sources. Request Acknowledge...
Page 199: Register Description
Atmel AVR XMEGA AU 15.10 Register Description 15.10.1 CTRLA – Control register A +0x00 – – – – CLKSEL[3:0] CTRLA Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 200 Atmel AVR XMEGA AU 15.10.3 CTRLC – Control register C +0x02 HCMPD HCMPC HCMPB HCMPA LCMPD LCMPC LCMPB LCMPA CTRLC Read/Write Initial Value • Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF.
Page 201 Atmel AVR XMEGA AU • Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level These bits enable the high-byte timer underflow interrupt and select the interrupt level, as described in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134. The enabled interrupt will be triggered when HUNFIF in the INTFLAGS register is set.
Page 202 Atmel AVR XMEGA AU • Bit 1:0 – CMDEN[1:0]: Command Enable These bits are used to indicate for which timer/counter the command (CMD) is valid. Table 15-5. Command selections. Group Configuration Description — Reserved Command valid for low-byte T/C HIGH...
Page 203 Atmel AVR XMEGA AU 15.10.10 HCNT – High-byte Count register +0x21 HCNT[7:0] HCNT Read/Write Initial Value • Bit 7:0 – HCNT[7:0] HCNT contains the eight-bit counter value for the high-byte timer/counter. The CPU and DMA write accesses have priority over count, clear, or reload of the counter.
Page 204 Atmel AVR XMEGA AU 15.10.14 HCMPx – High-byte Compare register x HCMPx[7:0] HCMPx Read/Write Initial Value • Bit 7:0 – HCMPx[7:0], x=[A, B, C, D] HCMPx contains the eight-bit compare value for the high-byte timer/counter. These registers are all continuously compared to the counter value. Normally the outputs from the comparators are then used for generating waveforms.
Page 205: Register Summary
Atmel AVR XMEGA AU 15.11 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRLA – – – – CLKSEL[3:0] +0x01 CTRLB HCMPDEN HCMPCEN HCMPBEN HCMPAEN LCMPDEN...
Page 206: Awex - Advanced Waveform Extension
Atmel AVR XMEGA AU 16. AWeX – Advanced Waveform Extension 16.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time –...
Page 207: Port Override
Atmel AVR XMEGA AU output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override set- ting.
Page 208: Dead-Time Insertion
Atmel AVR XMEGA AU Figure 16-2. Timer/counter extensions and port override logic. CWCM WG 0A OUT0 OC0A OCALS CCAEN INVEN0 OUTOVEN0 DTICCAEN Channel WG 0A OUTOVEN1 CCBEN INVEN1 OC0B OCAHS WG 0B OUT1 WG 0C OUT2 OC0C OCBLS CCCEN INVEN2...
Page 209: Pattern Generation
Atmel AVR XMEGA AU The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. Figure 16-3 on page 209 shows the block diagram of one DTI generator. The four channels have a common register that controls the dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double buffered.
Page 210: Fault Protection
Atmel AVR XMEGA AU cations. A block diagram of the pattern generator is shown in ”Pattern generator block diagram.” on page 210. For each port pin where the corresponding OOE bit is set, the multiplexer will out- put the waveform from CCA.
Page 211 Atmel AVR XMEGA AU 16.6.2 Fault Restore Modes How the AWeX and timer/counter return from the fault state to normal operation after a fault, when the fault condition is no longer active, can be selected from one of two different modes: •...
Page 212: Register Description
Atmel AVR XMEGA AU 16.7 Register Description 16.7.1 CTRL – Control register +0x00 – – CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN CTRL Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 213 Atmel AVR XMEGA AU • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 4 – FDDBD: Fault Detection on Debug Break Detection By default, when this bit is cleared and fault protection is enabled, and OCD break request is treated as a fault.
Page 214 Atmel AVR XMEGA AU • Bit 2 – FDF: Fault Detect Flag This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels enabled by FDEVMASK. This flag is cleared by writing a one to its bit location.
Page 215 Atmel AVR XMEGA AU • Bit 7:0 – DTLS: Dead-time Low Side This register holds the number of peripheral clock cycles for the dead-time low side. 16.7.8 DTHS – Dead-time High Side register +0x09 DTHS[7:0] DTHS Read/Write Initial Value • Bit 7:0 – DTHS: Dead-time High Side This register holds the number of peripheral clock cycles for the dead-time high side.
Page 216: Register Summary
Atmel AVR XMEGA AU • Bit 7:0 – OUTOVEN[7:0]: Output Override Enable These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position). The port direction is not overridden. 16.8 Register Summary Address Name...
Page 217: Hi-Res - High-Resolution Extension
Atmel AVR XMEGA AU 17. Hi-Res – High-Resolution Extension 17.1 Features • Increases waveform generator resolution up to 8x (3 bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 17.2...
Page 218: Register Description
Atmel AVR XMEGA AU The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than four will have no visible output. 17.3 Register Description 17.3.1 CTRLA – Control register A +0x00 –...
Page 219: Rtc - Real-Time Counter
Atmel AVR XMEGA AU 18. RTC – Real-Time Counter 18.1 Features • 16-bit resolution • Selectable clock source – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator • Programmable 10-bit clock prescaling •...
Page 220 Atmel AVR XMEGA AU 18.2.1 Clock Domains The RTC is asynchronous, operating from a different clock source independently of the main system clock and its derivative clocks, such as the peripheral clock. For control and count regis- ter updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change has effect on the RTC.
Page 221: Register Descriptions
Atmel AVR XMEGA AU 18.3 Register Descriptions 18.3.1 CTRL – Control register +0x00 – – – – – PRESCALER[2:0] CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 222 Atmel AVR XMEGA AU 18.3.2 STATUS – Status register +0x01 – – – – – – – SYNCBUSY STATUS Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 223 Atmel AVR XMEGA AU – 18.3.4 INTFLAGS Interrupt Flag register +0x03 – – – – – – COMPIF OVFIF INTFLAGS Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 224 Atmel AVR XMEGA AU – • Bit 7:0 CNT[7:0]: Counter Value Low These bits hold the LSB of the 16-bit real-time counter value. 18.3.7 CNTH – Counter Register High +0x09 CNT[15:8] CNTH Read/Write Initial Value • Bit 7:0 – CNT[15:8]: Counter Value High These bits hold the MSB of the 16-bit real-time counter value.
Page 225 Atmel AVR XMEGA AU 18.3.10 COMPL – Compare Register Low The COMPH and COMPL register pair represent the 16-bit value, COMP. COMP is constantly compared with the counter value (CNT). A compare match will set COMPIF in the INTFLAGS register. Reading and writing 16-bit values requires special attention. Refer ”Accessing 16-bit...
Page 226: Register Summary
Atmel AVR XMEGA AU 18.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – PRESCALER[2:0] +0x01 STATUS – – – –...
Page 227: Rtc32 - 32-Bit Real-Time Counter
Atmel AVR XMEGA AU 19. RTC32 – 32-bit Real-Time Counter 19.1 Features • 32-bit resolution • 32.768kHz external crystal clock source with selectable prescaling – 1.024kHz – 1Hz • One compare register • One period register • Clear counter on period overflow •...
Page 228 Atmel AVR XMEGA AU The Peripheral clock must be more than eight times faster than the RTC32 clock (1.024kHz or 1Hz) when any of the Control or the Count register are accessed (read or written), more than 12 times faster when the Count register is written.
Page 229: Register Descriptions
Atmel AVR XMEGA AU 19.3 Register Descriptions 19.3.1 CTRL – Control register +0x00 – – – – – – – ENABLE CTRL Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 230 Atmel AVR XMEGA AU 19.3.3 INTCTRL – Interrupt Control register +0x02 – – – – COMPINTLVL[1:0] OCINTLVL[1:0] INTCTRL Read/Write Reset Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 231 Atmel AVR XMEGA AU Synchronization of a new CNT value to the RTC32 domain is triggered by writing CNT3. The synchronization time is up to 12 peripheral clock cycles from updating the register until this has an effect in the RTC32 domain. Write operations to the CNT register will be blocked if the SYN- CBUSY flag is set.
Page 232 Atmel AVR XMEGA AU After writing a byte in the PER register, the write (HW/SW) condition for setting OVFIF and the overflow wake-up condition are disabled for the following two RTC32 clock cycles. +0x08 PER[7:0] PER0 Read/Write Initial Value 19.3.10 PER1 –...
Page 233 Atmel AVR XMEGA AU +0x0C COMP[7:0] COMP0 Read/Write Initial Value 19.3.14 COMP1 – Compare register 1 +0x0D COMP[15:8] COMP1 Read/Write Initial Value 19.3.15 COMP2 – Compare register 2 +0x0E COMP[23:16] COMP2 Read/Write Initial Value 19.3.16 COMP3 – Compare register 3...
Page 234: Register Summary
Atmel AVR XMEGA AU 19.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page – – – – – – – +0x00 CTRL ENABLE – – – –...
Page 235: Usb - Universal Serial Bus Interface
Atmel AVR XMEGA AU 20. USB – Universal Serial Bus Interface 20.1 Features • USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints –...
Page 236 Atmel AVR XMEGA AU To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA con- troller can then read/write one data buffer while the USB module writes/reads the others, and vice versa.
Page 237: Operation
Atmel AVR XMEGA AU 20.3 Operation This section gives an overview of the USB module operation during normal transactions. For general details on USB and the USB protocol, please refer to http://www.usb.org and the USB specification documents. 20.3.1 Start of Frame...
Page 238 Atmel AVR XMEGA AU Finally, the setup transaction complete flag (SETUP), data buffer 0 not acknowledge flag (NACK0), and data toggle flag (TOGGLE) are set, while the remaining flags in the endpoint sta- tus register (STATUS) are cleared for the addressed input and output endpoints. The setup transaction complete interrupt flag (SETUPIF) in INTFLAGSBCLR/SET is set.
Page 239 Atmel AVR XMEGA AU The incoming data are written to the data buffer pointed to by DATAPTR. If a bit-stuff error is detected in the incoming data, the USB module returns to idle and waits for the next token packet. If the number of received data bytes exceeds the maximum data payload specified by SIZE, the remaining received data bytes are discarded.
Page 240: Sram Memory Mapping
Atmel AVR XMEGA AU BUSNACK0 and TRNCOMPL0 are set and TOGGLE is toggled. TRNIF is set and the endpoint's configuration table address is written to the FIFO if the transcation complete FIFO mode is enabled. When an IN token is detected and the device address of the token packet does not match that of the endpoint, the packet is discarded and the USB module returns to idle and waits for the next token packet.
Page 241: Clock Generation
Atmel AVR XMEGA AU Figure 20-6. SRAM memory mapping. EP_ADDRH_MAX FIFO (MAXEP+1) x 4 Bytes Active when FIFOEN==1 EP_ADDRH_0 EP_ADDRL_0 EPPTR 0x00 STATUS ENDPOINT 0x01 CTRL DESCRIPTORS 0x02 CNTL ENDPOINT TABLE 0x03 CNTH 0 OUT 0x04 DATAPTRL 0x05 DATAPTRH 0x06...
Page 242: Ping-Pong Operation
Atmel AVR XMEGA AU Figure 20-7. Clock generation configuration. USBSRC 48MHz full speed USB clock USB module prescaler 6MHz for low speed 48MHz Internal Oscillator USBPSDIV 20.6 Ping-pong Operation When an endpoint is configured for ping-pong operation, it uses the input and output data buf- fers to create a single, double-buffered endpoint that can be set to input or output direction.
Page 243: Multipacket Transfers
Atmel AVR XMEGA AU Figure 20-8. Ping-pong operation overview. Endpoint single bank Without Ping-Pong Endpoint Double bank With Ping-Pong Bank0 Bank1 USB data packet Available time for data processing by CPU to avoid NACK 20.7 Multipacket Transfers Multipacket transfer enables a data payload exceeding the maximum data payload size of an endpoint to be transferred as multiple packets without any software intervention.
Page 244: Auto Zero Length Packet
Atmel AVR XMEGA AU When an IN token is received, the endpoint’s CNT and AUXDATA are fetched. If CNT minus AUXDATA is less than the endpoint SIZE, endpoint CNT minus endpoint AUXDATA number bytes are transmitted; otherwise, SIZE number of bytes are transmitted. If endpoint CNT is a multiple of SIZE and auto zero length packet (AZLP) is enabled, the last packet sent will be zero length.
Page 245: Interrupts And Events
Atmel AVR XMEGA AU Figure 20-10. Transfer complete FIFO. INTERNAL SRAM EPPTR – TC_ EP_ ADDRH _ MAX 4x( MAXEP +1) USB_ TC_ FIFO TC_ EP_ ADDRH_2 TC_ EP_ ADDRH_2 FIFOWP TC_EP_ ADDRL_1 TC_ EP_ ADDRH_1 TC_EP_ ADDRL_0 FIFORP TC _ EP _ ADDRH_0...
Page 246 Atmel AVR XMEGA AU Figure 20-12 on page 246 summarizes the interrupts and event sources for the USB module, and shows how they are enabled. Figure 20-12. Interrupts and events scheme summary. SOFIF SUSPENDIF SOFIE RESUMEIF RSTIF BSEVIE Busevent Interrupt request...
Page 247: Vbus Detection
Underflow/overflow UNFIF and OVFIF 20.11 VBUS Detection Atmel AVR XMEGA devices can use any general purpose I/O pin to implement a VBUS detec- tion function, and do not use a dedicated VBUS detect pin. 20.12 On-chip Debug When a break point is reached during on-chip debug (OCD) sessions, the CPU clock can be below 12MHz.
Page 248: Register Description - Usb
Atmel AVR XMEGA AU 20.13 Register Description – USB 20.13.1 CTRLA – Control register A +0x00 ENABLE SPEED FIFOEN STFRNUM MAXEP[3:0] CTRLA Read/Write Initial Value • Bit 7 – ENABLE: USB Enable Setting this bit enables the USB interface. Clearing this bit disables the USB interface and imme- diately aborts any ongoing transactions.
Page 249 Atmel AVR XMEGA AU • Bit 4 – PULLRST: Pull during Reset Setting this bit enables the pull-up on the USB lines to also be held when the device enters reset. The bit will be cleared on a power-on reset.
Page 250 Atmel AVR XMEGA AU 20.13.4 ADDR – Address register +0x03 – ADDR[6:0] ADDR Read/Write Initial Value • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Page 251 Atmel AVR XMEGA AU 20.13.7 EPPTRL – Endpoint Configuration Table Pointer Low Byte The EPPTRL and EPPTRH registers represent the 16-bit value, EPPTR, that contains the address to the endpoint configuration table. The pointer to the endpoint configuration table must be aligned to a 16-bit word;...
Page 252 Atmel AVR XMEGA AU • Bit 5 – BUSERRIE: Bus Error Interrupt Enable Setting this bit will enable the interrupt for the following three bus error events: 1. Isochronous CRC Error: An interrupt will be generated for the conditions that set the CRC interrupt flag (CRCIF) in the INTFLAGSACLR/SET register during isochronous transfers.
Page 253 Atmel AVR XMEGA AU FLAGSACLR. Both memory locations will provide the same result when read, and writing zero to any bit location has no effect. +0x0A/ +0x0B SOFIF SUSPENDIF RESUMEIF RESETIF CRCIF UNFIF OVFIF STALLIF Read/Write Initial Value • Bit 7 – SOFIF: Start Of Frame Interrupt Flag This flag is set when a start of frame packet has been received.
Page 254 Atmel AVR XMEGA AU • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 – TRNIF: Transaction Complete Interrupt Flag This flag is when there is a pending packet interrupt in the FIFO.
Page 255: Register Description - Usb Endpoint
Atmel AVR XMEGA AU 20.14 Register Description USB Endpoint – Each of the 16 endpoint addresses have one input and one output endpoint. Each endpoint has eight bytes of configuration/status data located in internal SRAM. The address to the first configuration byte is (EPPTR[15:0] + 16 × endpoint address) for output endpoints and (EPPTR[15:0] + 16 ×...
Page 256 Atmel AVR XMEGA AU • Bit 3 – BANK: Bank Select Flag When ping-pong mode is enabled, this bit indicates which bank will be used for the next transac- tion. BANK is toggled each time a transaction has completed successfully. This bit is not sed when ping-pong is disabled.
Page 257 Atmel AVR XMEGA AU interrupts or software intervention. See ”Multipacket Transfers” on page 243 for details on multi- packet transfers. • Bit 4 – PINGPONG: Ping-pong Enable Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN and OUT) with same address to be used in the same direction to allow double buffering and maximize throughput.
Page 258 Atmel AVR XMEGA AU +0x02 CNT[7:0] CNTL Read/Write Initial Value • Bit 7:0 – CNT[7:0]: Endpoint Byte Counter This byte contains the eight lsbs of the USB endpoint counter (CNT). 20.14.4 CNTH – Counter High +0x03 AZLP – – –...
Page 259 Atmel AVR XMEGA AU • Bit 15:0 - DPTR[15:8]: Endpoint Data Pointer High This byte contains the eight msbs of the endpoint data pointer (DATAPTR). 20.14.7 AUXDATAL – Auxiliary Data Low The AUXDATAL and AUXDATAH registers represent the 16-bit value, AUXDATA, that is used for multipacket transfers.
Page 260: Register Description - Frame
Atmel AVR XMEGA AU 20.15 Register Description – Frame 20.15.1 FRAMENUML – Frame Number Low The FRAMENUML and FRAMENUMH registers represent the 11-bit value, FRAMENUM, that holds the frame number from the most recently received start of frame packet. +0x00...
Page 261: Register Summary - Usb Module
Atmel AVR XMEGA AU 20.16 Register Summary – USB Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRLA ENABLE SPEED FIFOEN STFRNUM MAXEP[3:0] +0x01 CTRLB – –...
Page 262: Twi - Two-Wire Interface
Atmel AVR XMEGA AU 21. TWI – Two-Wire Interface 21.1 Features • Bidirectional, two-wire communication interface – Phillips I C compatible – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – Single bus master operation –...
Page 263: General Twi Bus Concepts
Atmel AVR XMEGA AU 21.3 General TWI Bus Concepts The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up resistors provide a high level on the lines when none of the connected devices are driving the The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
Page 264 Atmel AVR XMEGA AU Figure 21-2. Basic TWI transaction diagram topology for a 7-bit address bus . 6 ... 0 7 ... 0 7 ... 0 ADDRESS DATA DATA ACK/NACK ADDRESS DATA DATA Direction Address Packet Data Packet #0 Data Packet #1...
Page 265 Atmel AVR XMEGA AU 21.3.3 Bit Transfer As illustrated by Figure 21-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line. Consequently the SDA value can only be changed during the low period of the clock.
Page 266 Atmel AVR XMEGA AU Figure 21-5. Master write transaction. Transaction Address Packet Data Packet ADDRESS DATA DATA N data packets Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP condition (P) directly after the address packet.
Page 267 Atmel AVR XMEGA AU Three types of clock stretching can be defined, as shown in Figure 21-8. Figure 21-8. Clock stretching bit 7 bit 6 bit 0 ACK/NACK Wakeup clock Periodic clock Random clock stretching stretching stretching Note: 1. Clock stretching is not supported by all I C slaves and masters.
Page 268: Twi Bus State Logic
Atmel AVR XMEGA AU Figure 21-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Page 269: Twi Master Operation
Atmel AVR XMEGA AU Figure 21-11. Bus state, state diagram. RESET UNKNOWN (0b00) P + Timeout IDLE BUSY P + Timeout (0b01) (0b11) Command P Arbitration Write ADDRESS Lost OWNER (0b10) Write ADDRESS(Sr) After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter idle by writing to the bus state bits accordingly.
Page 270 Atmel AVR XMEGA AU When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and will in most cases require software interaction. Figure 21-12 shows the TWI master operation.
Page 271: Twi Slave Operation
Atmel AVR XMEGA AU 21.5.1.2 Case M2: Address packet transmit complete - Address not acknowledged by slave If no slave device responds to the address, the master write interrupt flag and the master received acknowledge flag are set. The clock hold is active at this point, preventing further activ- ity on the bus.
Page 272 Atmel AVR XMEGA AU Figure 21-13. TWI slave operation. SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT ADDRESS DATA Driver software DATA The master provides data on the bus Interrupt on STOP Condition Enabled Slave provides data on the bus Collision Release...
Page 273: Enabling External Driver Interface
Atmel AVR XMEGA AU received. Data, repeated START, or STOP can be received after this. If NACK is sent, the slave will wait for a new START condition and address match. 21.6.1.3 Case S3: Collision If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge output from the slave logic.
Page 274: Register Description - Twi
Atmel AVR XMEGA AU 21.8 Register Description – TWI 21.8.1 CTRL – Common Control Register +0x00 – – – – – SDAHOLD[1:0] EDIEN CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 275: Register Description - Twi Master
Atmel AVR XMEGA AU 21.9 Register Description – TWI Master – 21.9.1 CTRLA Control register A +0x00 INTLVL[1:0] RIEN WIEN ENABLE – – – CTRLA Read/Write Initial Value – • Bit 7:6 INTLVL[1:0]: Interrupt Level These bits select the interrupt level for the TWI master interrupt, as described in ”Interrupts and...
Page 276 Atmel AVR XMEGA AU Table 21-3. TWI master inactive bus timeout settings. TIMEOUT[1:0] Group Configuration Description DISABLED Disabled, normally used for I 50US 50µs, normally used for SMBus at 100kHz 100US 100µs 200US 200µs – • Bit 1 QCEN: Quick Command Enable When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address (read or write interrupt).
Page 277 Atmel AVR XMEGA AU STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Table 21-5. CMD bits description. Group CMD[1:0]...
Page 278 Atmel AVR XMEGA AU – • Bit 5 CLKHOLD: Clock Hold This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.
Page 279 Atmel AVR XMEGA AU The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency. The frequency relation can be expressed by using the following equation: --------------------------------------- - [Hz] BAUD The BAUD register must be set to a value that results in a TWI bus clock frequency (f...
Page 280: Register Description - Twi Slave
Atmel AVR XMEGA AU register can only be accessed when the SCL line is held low by the master; i.e., when CLKHOLD is set. In master write mode, writing the DATA register will trigger a data byte transfer followed by the master receiving the acknowledge bit from the slave.
Page 281 Atmel AVR XMEGA AU – • Bit 0 SMEN: Smart Mode Enable This bit enables smart mode. When Smart mode is enabled, the acknowledge action, as set by the ACKACT bit in the CTRLB register, is sent immediately after reading the DATA register.
Page 282 Atmel AVR XMEGA AU Table 21-8. TWI slave command. (Continued) Group CMD[1:0] Configuration Operation Used in response to an address byte (APIF is set) Execute acknowledge action succeeded by reception of next byte Execute acknowledge action succeeded by DIF being set...
Page 283 Atmel AVR XMEGA AU – • Bit 4 RXACK: Received Acknowledge This flag contains the most recently received acknowledge bit from the master. This is a read- only flag. When read as zero, the most recent acknowledge bit from the maser was ACK, and when read as one, the most recent acknowledge bit was NACK.
Page 284 Atmel AVR XMEGA AU When using 10-bit addressing, the address match logic only supports hardware address recog- nition of the first byte of a 10-bit address. By setting ADDR[7:1] = 0b11110nn, ”nn” represents bits 9 and 8 of the slave address. The next byte received is bits 7 to 0 in the 10-bit address, and this must be handled by software.
Page 285 Atmel AVR XMEGA AU mask bit is one, the address match between the incoming address bit and the corresponding bit in ADDR is ignored; i.e., masked bits will always match. If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to the ADDR register.
Page 286: Register Summary - Twi
Atmel AVR XMEGA AU 21.11 Register Summary - TWI Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – SDAHOLD EDIEN +0x01 MASTER Offset address for TWI Master...
Page 287: Spi - Serial Peripheral Interface
Atmel AVR XMEGA AU 22. SPI – Serial Peripheral Interface 22.1 Features • Full-duplex, three-wire synchronous data transfer • Master or slave operation • Lsb first or msb first data transfer • Eight programmable bit rates • Interrupt flag at the end of transmission •...
Page 288: Master Mode
Atmel AVR XMEGA AU When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 22-1. The pins with user-defined direction must be configured from software to have the correct direction according to the application.
Page 289: Data Modes
Atmel AVR XMEGA AU 22.5 Data Modes There are four combinations of SCK phase and polarity with respect to serial data. The SPI data transfer formats are shown in Figure 22-2. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
Page 290: Register Description
Atmel AVR XMEGA AU 22.7 Register Description 22.7.1 CTRL – Control register +0x00 CLK2X ENABLE DORD MASTER MODE[1:0] PRESCALER[1:0] CTRL Read/Write Initial Value • Bit 7 – CLK2X: Clock Double When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see...
Page 291 Atmel AVR XMEGA AU Table 22-3. Relationship between SCK and the peripheral clock (Clk ) frequency. CLK2X PRESCALER[1:0] SCK Frequency /128 22.7.2 INTCTRL – Interrupt Control register +0x01 – – – – – – INTLVL[1:0] INTCTRL Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use.
Page 292: Register Summary
Atmel AVR XMEGA AU • Bit 6 – WRCOL: Write Collision Flag The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared by first reading the STATUS register when WRCOL is set, and then accessing the DATA register.
Page 293: Usart
Atmel AVR XMEGA AU 23. USART 23.1 Features • Full-duplex operation • Asynchronous or synchronous operation – Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency •...
Page 294 Atmel AVR XMEGA AU Figure 23-1. USART block diagram. Clock Generator BSEL [H:L] BAUD RATE GENERATOR FRACTIONAL DIVIDE SYNC LOGIC CONTROL Transmitter DATA (Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RECOVERY...
Page 295: Clock Generation
Atmel AVR XMEGA AU 23.3 Clock Generation The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported: normal and double-speed asynchronous mode, master and slave synchronous mode, and master SPI mode.
Page 296 Atmel AVR XMEGA AU Table 23-1. Equations for calculating baud rate register settings. Operating Mode Conditions Baud Rate Calculation BSEL Value Calculation BSCALE ≥ 0 ------------------------------------------------ 1 – BSEL ------------------------------------------------------------- - ≤ BAUD ---------- - BSCALE BSCALE ⋅ ⋅ Asynchronous normal...
Page 297 Atmel AVR XMEGA AU 23.3.3 Double Speed Operation Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock frequencies. When this is enabled, the baud rate for a given asynchronous baud rate setting shown in Table 23-1 on page 296 will be doubled.
Page 298: Frame Formats
Atmel AVR XMEGA AU Table 23-2. INVEN and UCPHA functionality. SPI Mode INVEN UCPHA Leading Edge Trailing Edge Rising, sample Falling, setup Rising, setup Falling, sample Falling, sample Rising, setup Falling, setup Rising, sample The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Page 299: Usart Initialization
Atmel AVR XMEGA AU Figure 23-5. Frame formats. FRAME (IDLE) Sp1 [Sp2] (St / IDLE) Start bit, always low. Data bits (0 to 8). Parity bit, may be odd or even. Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). The IDLE state is always high.
Page 300: Data Reception - The Usart Receiver
Atmel AVR XMEGA AU 23.6.1 Sending Frames A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent. The data in the transmit buffer are moved to the shift register when the shift register is empty and ready to send a new frame.
Page 301: Asynchronous Data Reception
Atmel AVR XMEGA AU 23.7.3 Parity Checker When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set.
Page 302 Atmel AVR XMEGA AU 23.8.2 Asynchronous Data Recovery The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit. Figure 23-7 on page 302 shows the sampling process of data and parity bits.
Page 303 Atmel AVR XMEGA AU ------------------------------------------ - ----------------------------------- D S ⋅ slow fast – Sum of character size and parity size (D = 5 to 10 bits). Samples per bit. S = 16 for normal speed mode and S = 8 for double speed mode.
Page 304: Fractional Baud Rate Generation
Atmel AVR XMEGA AU 23.9 Fractional Baud Rate Generation Fractional baud rate generation is possible for asynchronous operation due to the relatively high number of clock cycles for each frame. Each bit is sampled sixteen times, but only the three mid- dle samples are of importance.
Page 305 Atmel AVR XMEGA AU Figure 23-9. Fractional baud rate example. BSEL=0 BSCALE=0 BAUD BAUD8 BSEL=3 BSCALE=-6 /8.375 BAUD BAUD8 Extra clock cycle added BSEL=3 BSCALE=-4 /9.5 BAUD BAUD8 8331B–AVR–03/12...
Page 306 Atmel AVR XMEGA AU Table 23-5. USART Baud rate. Baud = 32.0000MHz CLK2X = 0 CLK2X = 1 rate (bps) BSEL BSCALE Error [%] BSEL BSCALE Error [%] 2400 4800 9600 14.4k -0.1 -0.1 19.2k -0.8 -0.8 28.8k -0.1 -0.1 38.4k...
Page 307: Usart In Master Spi Mode
Atmel AVR XMEGA AU 23.10 USART in Master SPI Mode Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to serve as the serial input. The XCK pin will be used as the transfer clock.
Page 308: Ircom Mode Of Operation
Atmel AVR XMEGA AU If the receiver is set up to receive frames that contain five to eight data bits, the first stop bit is used to indicate the frame type. If the receiver is set up for frames with nine data bits, the ninth bit is used.
Page 309: Register Description
Atmel AVR XMEGA AU 23.15 Register Description 23.15.1 DATA – Data register RXB[[7:0] +0x00 TXB[[7:0] Read/Write Initial Value The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB) share the same I/O address and is referred to as USART data register (DATA). The TXB register is the destination for data written to the DATA register location.
Page 310 Atmel AVR XMEGA AU • Bit 5 – DREIF: Data Register Empty Flag This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is one when the transmit buffer is empty and zero when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register.
Page 311 Atmel AVR XMEGA AU 23.15.3 CTRLA – Control register A +0x03 – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] CTRLA Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 312 Atmel AVR XMEGA AU shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. • Bit 2 – CLK2X: Double Transmission Speed Setting this bit will reduce the divisor of the baud rate divider from16 to 8, effectively doubling the transfer rate for asynchronous communication modes.
Page 313 Atmel AVR XMEGA AU • Bits 5:4 – PMODE[1:0]: Parity Mode These bits enable and set the type of parity generation according to Table 23-8 on page 313. When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame.
Page 314 Atmel AVR XMEGA AU • Bit 2 – UDORD: Data Order This bit is only for master SPI mode, and this bit sets the frame format. When written to one, the lsb of the data word is transmitted first. When written to zero, the msb of the data word is trans- mitted first.
Page 315: Register Summary
Atmel AVR XMEGA AU 23.16 Register Summary 23.16.1 Register Description - USART Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 DATA DATA[7:0] +0x01 STATUS RXCIF TXCIF DREIF FERR...
Page 316: Ircom - Ir Communication Module
Atmel AVR XMEGA AU 24. IRCOM - IR Communication Module 24.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable –...
Page 317 Atmel AVR XMEGA AU For transmission, three pulse modulation schemes are available: • 3/16 of the baud rate period • Fixed programmable pulse time based on the peripheral clock frequency • Pulse modulation disabled For reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical 0 is used.
Page 318: Registers Description
Atmel AVR XMEGA AU 24.3 Registers Description 24.3.1 TXPLCTRL – Transmitter Pulse Length Control Register +0x01 TXPLCTRL[7:0] TXPLCTRL Read/Write Initial Value • Bit 7:0 – TXPLCTRL[7:0]: Transmitter Pulse Length Control This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have no effect if IRCOM mode is not selected by a USART.
Page 319: Register Summary
Atmel AVR XMEGA AU • Bit 3:0 – EVSEL [3:0]: Event Channel Selection These bits select the event channel source for the IRCOM receiver according to Table 24-1 on page 319. If event input is selected for the IRCOM receiver, the input from the USART’s RX pin is automatically disabled.
Page 320: Aes And Des Crypto Engines
Atmel AVR XMEGA AU 25. AES and DES Crypto Engines 25.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per 8-byte block •...
Page 321: Aes Crypto Module
Atmel AVR XMEGA AU Figure 25-1. Register file usage during DES encryption/decryption. Register File data0 data1 data2 data3 data4 data5 data6 data7 key0 key1 key2 key3 key4 key5 key6 key7 Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext.
Page 322 Atmel AVR XMEGA AU The following setup and use procedure is recommended: 1. Enable the AES interrupt (optional). 2. Select the AES direction to encryption or decryption. 3. Load the key data block into the AES key memory. 4. Load the data block into the AES state memory.
Page 323 Atmel AVR XMEGA AU Figure 25-3. The key memory with pointers and register. 4-bit key read address pointer Reset pointer 4-bit key write reset or address pointer access to CTRL Reset pointer reset or access to CTRL In the AES crypto module, the following definition of the key is used: •...
Page 324: Register Description - Aes
Atmel AVR XMEGA AU 25.5 Register Description – AES – 25.5.1 CTRL Control register +0x00 START AUTO RESET DECRYPT – – – CTRL Read/Write Initial Value – • Bit 7 START: Start/Run Setting this bit starts the encryption/decryption procedure, and this bit remains set while the encryption/decryption is ongoing.
Page 325 Atmel AVR XMEGA AU – • Bit 1:0 Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. – 25.5.2 STATUS AES Status register...
Page 326 Atmel AVR XMEGA AU – 25.5.4 Key register +0x03 KEY[7:0] Read/Write Initial Value The KEY register is used to access the key memory. Before encryption/decryption can take place, the key memory must be written sequentially, byte-by-byte, through the KEY register.
Page 327: Register Summary - Aes
Atmel AVR XMEGA AU 25.6 Register Summary - AES Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL START AUTO RESET DECRYPT – – – +0x01 STATUS ERROR –...
Page 328: Crc - Cyclic Redundancy Check Generator
Atmel AVR XMEGA AU 26. CRC – Cyclic Redundancy Check Generator 26.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space •...
Page 329: Operation
Atmel AVR XMEGA AU 26.3 Operation The data source for the CRC module must be selected in software as either flash memory, the DMA channels, or the I/O interface. The CRC module then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CHECKSUM registers in the CRC module.
Page 330: Crc On Dma Data
Atmel AVR XMEGA AU 26.5 CRC on DMA Data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC module will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted.
Page 331: Register Description
Atmel AVR XMEGA AU 26.7 Register Description 26.7.1 CTRL – Control register +0x00 RESET[1:0] CRC32 – SOURCE[3:0] CTRL Read/Write Initial Value • Bit 7:6 – RESET[1:0]: Reset These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be reset one peripheral clock cycle after the RESET[1] bit is set.
Page 332 Atmel AVR XMEGA AU Table 26-2. CRC source select (Continued). SOURCE[3:0] Group configuration Description 0110 DMACH2 DMA controller channel 2 0111 DMACH3 DMA controller channel 3 1xxx — Reserved for future use 26.7.2 STATUS – Status register +0x02 – –...
Page 333 Atmel AVR XMEGA AU 26.7.4 CHECKSUM0 – Checksum Byte 0 CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit CHECKSUM value and the generated CRC. The registers are reset to zero by default, but it is possible to write RESET to reset all bits to one. It is possible to write these registers only when the CRC module is disabled.
Page 334: Register Sumary
Atmel AVR XMEGA AU • Bit 7:0 – CHECKSUM[31:24] These bits hold byte 3 of the generated CRC when CRC-32 is used. 26.8 Register Sumary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 335: Ebi - External Bus Interface
Atmel AVR XMEGA AU 27. EBI – External Bus Interface 27.1 Features • Supports SRAM up to: – 512KB using 2-port EBI – 16MB using 3-port EBI • Supports SDRAM up to: – 128Mb using 3-port EBI • Four software configurable chip selects •...
Page 336 Atmel AVR XMEGA AU 27.3.1 Base Address The base address assigned to a chip select is the lowest address in the address space, and determines the first location in data memory space where the connected memory hardware can be accessed. The base address associated with each chip select must be on a 4KB boundary.
Page 337: Ebi Clock
Atmel AVR XMEGA AU 27.4 EBI Clock The EBI is clocked from the Peripheral 2x (Clk ) Clock. This clock can run at the CPU Clock PER2 frequency, or at two times the CPU Clock frequency. This can be used to lower the EBI access time.
Page 338 Atmel AVR XMEGA AU Figure 27-4. Multiplexed SRAM connection using ALE1. D[7:0] D[7:0] A[15:8]/ A[7:0] A[7:0] SRAM A[15:8] ALE1 A[19:16] A[19:16] 27.5.3 Multiplexing address byte 0 and 2 When address byte 0 (A[7:0]) and address byte 2 (A[23:16) are multiplexed, they are output from the same port, and the ALE2 signal from the device controls the address latch.
Page 339: Sram Lpc Configuration
Atmel AVR XMEGA AU 27.5.5 Address Latches The Address Latch timing and parameter requirements are described in EBI Timing. See the device datasheet characteristics for details. To reduce access time when using multiplexing of address, the ALE signals are only issued when it is required to update the latched address. For instance if address lines A[15:8] are multiplexed with A[7:0] the ALE1 and A[15:8] are only given if any bit in A[15:8] are changed since the last time ALE was set.
Page 340: Sdram Configuration
Atmel AVR XMEGA AU Figure 27-8. Multiplexed SRAM LPC connection using ALE1 and ALE2. A[15:8]/ D[7:0] AD[7:0] A[7:0] SRAM ALE1 A[15:8] ALE2 A[19:16] A[19:16] 27.7 SDRAM Configuration Chip Select 3 on the EBI can be configured from SDRAM operation, and the EBI must be config- ured as a three-port or four-port interface.
Page 341 Atmel AVR XMEGA AU Table 27-3. Supported SDRAM commands. (Continued) AUTO REFRESH Refresh one row of each bank LOAD MODE Load mode register SELF REFRESH Activate self refresh mode 27.7.2 Three-Port EBI Configuration When three EBI ports are available, SDRAM can be connected with a three-Port EBI configura- tion.
Page 342: Combined Sram & Sdram Configuration
Atmel AVR XMEGA AU 27.7.4 Timing The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU clock speed. 27.7.5 Initialization Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The Load Mode Register command is automatically issued at the end of the initialization.
Page 343: I/O Pin And Pin-Out Configuration
Atmel AVR XMEGA AU Figure 27-11. Combined SRAM and SDRAM connection BA[1:0] BA[1:0] RAS/ALE1 SDRAM CAS/RE D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] A[11:8]/A[19:16] A[11:8] CS[3:0] D[7:0] SRAM A[7:0] A[15:8] A[19:16] 27.9 I/O Pin and Pin-out Configuration When the EBI is enabled, it will override the direction and/or value of the I/O pins where the EBI data lines are placed.
Page 344 Atmel AVR XMEGA AU Table 27-4. Pin-out SRAM. PORT SRAM SRAM SRAM SRAM 3PORT 3PORT 4PORT 4PORT ALE1 ALE12 ALE2 NOALE – – PORT3 A[15:8] A[15:8] PORT2 A[7:0]/ A[7:0]/ A[7:0]/ A[7:0] A[15:8] A[15:8]/ A[23:16] A[23:16] PORT1 D[7:0] D[7:0] D[7:0] D[7:0]...
Page 345 Atmel AVR XMEGA AU Table 27-6. Pin-out for SRAM and SRAM LPC when combined with SDRAM (four-port only). PORT SRAM LPC SRAM LPC SRAM SRAM ALE1 ALE12 ALE1 ALE12 (with SDRAM) (with SDRAM) (with SDRAM) (with SDRAM) CS[3:0] CS[3:0] CS[3:0]...
Page 346: Register Description - Ebi
Atmel AVR XMEGA AU 27.10 Register Description – 27.10.1 CTRL – Control register +0x00 SDDATAW[1:0] LPCMODE[1:0] SRMODE[1:0] IFMODE[1:0] CTRL Read/Write Initial Value • Bit 7:6 – SDDATAW[1:0]: SDRAM Data Width Setting These bits select the EBI SDRAM data width configuration, according to Table 27-8 on page 346.
Page 347 Atmel AVR XMEGA AU • Bit 1:0 – IFMODE[1:0]: Interface Mode These bits select EBI interface mode and the number of ports that should be enabled and over- ridden for EBI, according to Table 27-11 on page 347. Table 27-11. EBI Mode...
Page 348 Atmel AVR XMEGA AU Table 27-14. SDRAM column bits. SDCOL[1:0] Group Configuration Description 8BIT 8 column bits 9BIT 9 column bits 10BIT 10 column bits 11BIT 11 column bits 27.10.3 REFRESH – SDRAM Refresh Period Register +0x04 REFRESH[7:0] REFRESHL Read/Write...
Page 349 Atmel AVR XMEGA AU • Bit 13:0 – INITDLY[13:0]: SDRAM Initialization Delay This register is used to delay the initialisation sequence after the controller is enabled until all voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM chip through its initialisation sequence.
Page 350 Atmel AVR XMEGA AU Table 27-17. SDRAM row to precharge delay settings RPDLY[2:0] Group Configuration Description 0CLK Zero Clk cycles delay PER2 1CLK One Clk cycles delay PER2 2CLK Two Clk cycles delay PER2 3CLK Three Clk cycles delay PER2...
Page 351: Register Description - Ebi Chip Select
Atmel AVR XMEGA AU Table 27-19. SDRAM exit self-refresh delay settings. ESRDLY[2:0] Group Configuration Description 0CLK Zero Clk cycles delay PER2 1CLK One Clk cycles delay PER2 2CLK Two Clk cycles delay PER2 3CLK Three Clk cycles delay PER2 4CLK...
Page 352 Atmel AVR XMEGA AU Table 27-21. Address size encoding ASIZE[4:0] Group Configuration Address Size Address Lines Compared 00000 256B 256 bytes ADDR[23:8] 00001 512B 512 bytes ADDR[23:9] 00010 ADDR[23:10] 00011 ADDR[23:11] 00100 ADDR[23:12] 00101 ADDR[23:13] 00110 16KB ADDR[23:14 00111 32KB...
Page 353 Atmel AVR XMEGA AU 27.11.2 CTRLB (SRAM) – Control register B The configuration options for this register depend on the chip select mode configuration. The register description below is valid when the chip select mode is configured for SRAM or SRAM LPC.
Page 354 Atmel AVR XMEGA AU • Bit 1:0 SDMODE[1:0]: SDRAM Mode These bits select the mode when accessing SDRAM according to Table 27-24 on page 354. Table 27-24. SDRAM mode SDMODE[1:0] Group Configuration Description NORMAL Normal mode - access to the SDRAM is decoded normally...
Page 355: Register Summary - Ebi
Atmel AVR XMEGA AU 27.12 Register Summary - EBI Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL SDDATAW[1:0] LPCMODE[1:0] SRMODE[1:0] IFMODE[1:0] +0x01 SDRAMCTRLA – – – –...
Page 356: Adc - Analog-To-Digital Converter
Atmel AVR XMEGA AU 28. ADC – Analog-to-Digital Converter 28.1 Features • 12-bit resolution • Up to two million samples per second – Two inputs can be sampled simultaneously using ADC and 1x gain stage – Four inputs can be sampled within 1.5µs –...
Page 357: Input Sources
Atmel AVR XMEGA AU The ADC has a compare function for accurate monitoring of user defined thresholds with mini- mum software intervention required. Figure 28-1. ADC overview. S&H Σ ADC0 2 bits Compare • • • ADC15 Stage Stage Stage Internal <...
Page 358 Atmel AVR XMEGA AU Figure 28-2. Differential measurement without gain. ADC0 • • • ADC15 ADC0 • • • ADC3 INTGND 28.3.2 Differential Input with Gain When differential input with gain is enabled, all input pins can be selected as positive input, and input pins 4 to 7 can be selected as negative input.
Page 359 Atmel AVR XMEGA AU Figure 28-4. Single-ended measurement in signed mode. ADC0 • • • ADC15 In unsigned mode, the negative input is connected to half of the voltage reference (VREF) volt- age minus a fixed offset. The nominal value for the offset is: ΔV...
Page 360: Adc Channels
Atmel AVR XMEGA AU nal signals is lower than that of the ADC. Refer to the ADC characteristics in the device datasheets for details. For differential measurement Pad Ground (Gnd) and Internal Gnd can be selected as negative input. Pad Gnd is the gnd level on the pin and identical or very close to the external gnd. Internal Gnd is the internal device gnd level.
Page 361: Voltage Reference Selection
Atmel AVR XMEGA AU 28.5 Voltage Reference Selection The following voltages can be used as the reference voltage (VREF) for the ADC: • Accurate internal 1.00V voltage generated from the bandgap • Internal V /1.6V voltage • Internal V /2V voltage •...
Page 362 Atmel AVR XMEGA AU can be represented either left or right adjusted. Left adjusted means that the eight most-signifi- cant bits (msb) are found in the high byte. When the ADC is in signed mode, the msb represents the sign bit. In 12-bit right adjusted mode, the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number directly.
Page 363: Compare Function
Atmel AVR XMEGA AU 28.7 Compare Function The ADC has a built-in 12-bit compare function. The ADC compare register can hold a 12-bit value that represents a threshold voltage. Each ADC channel can be configured to automatically compare its result with this compare value to give an interrupt or event only when the result is above or below the threshold.
Page 364 Atmel AVR XMEGA AU RESOLUTION is the resolution, 8 or 12 bits. The propagation delay will increase by one extra ADC clock cycle if the gain stage (GAIN) is used. The propagation delay is longer than one ADC clock cycle, but the pipelined design means that the sample rate is limited not by the propagation delay, but by the ADC clock rate.
Page 365 Atmel AVR XMEGA AU Figure 28-14. ADC timing for one single conversion with gain. START GAINSTAGE SAMPLE GAINSTAGE AMPLIFY ADC SAMPLE CONVERTING BIT 28.9.3 Single Conversions on Two ADC Channels Figure 28-15 on page 365 shows the ADC timing for single conversions on two channels. The pipelined design enables the second conversion to start on the next ADC clock cycle after the first conversion has started.
Page 366 Atmel AVR XMEGA AU Figure 28-16. ADC timing for single conversion on two ADC channels, CH0 with gain. START CH0, w/GAIN START CH1, wo/GAIN GAINSTAGE SAMPLE GAINSTAGE AMPLIFY ADC SAMPLE IF CH0 IF CH1 CONVERTING BIT CH0 CONVERTING BIT CH1 28.9.5...
Page 367: Adc Input Model
Atmel AVR XMEGA AU done and available, and so on. In this mode, up to eight conversions are ongoing at the same time. Figure 28-18. ADC timing for free running mode. START CH0, wo/GAIN START CH1, wo/GAIN START CH0, w/GAIN...
Page 368: Dma Transfer
Atmel AVR XMEGA AU In order to achieve n bits of accuracy, the source output resistance, R , must be less than source the ADC input resistance on a pin: ≤ ---------------------------------------------- - R – – source channel switch ⋅...
Page 369: Synchronous Sampling
Atmel AVR XMEGA AU 28.15 Synchronous Sampling The ADC can be configured to do synchronous sampling in three different ways. 1. Sample two input channels at the same time 2. Sample two ADCs at the same time 3. Sample on external trigger 28.15.1...
Page 370: Register Description - Adc
Atmel AVR XMEGA AU 28.16 Register Description – 28.16.1 CTRLA – Control register A +0x00 DMASEL[1:0] CHSTART[3:0] FLUSH ENABLE CTRLA Read/Write Initial Value • Bit 7:6 – DMASEL[1:0]: DMA Request Selection To allow one DMA channel to serve more than one ADC channel, the DMA request from the channels can be combined into a common DMA request.
Page 371 Atmel AVR XMEGA AU Table 28-2. Gain stage impedance mode. IMPMODE Group Configuration Description HIGHIMP For high-impedance sources; charge will remain on input LOWIMP For low impedance sources • Bit 6:5 – CURRLIMIT[1:0]: Current Limitation These bits can be used to limit the current consumption of the ADC by reducing the maximum ADC sample rate.
Page 372 Atmel AVR XMEGA AU 28.16.3 REFCTRL – Reference Control register +0x02 – REFSEL[2:0] – – BANDGAP TEMPREF REFCTRL Read/Write Initial Value • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Page 373 Atmel AVR XMEGA AU Table 28-6. ADC channel select. SWEEP[1:0] Group Configuration Active ADC Channels for Channel Sweep Only ADC channel 0 ADC channels 0 and 1 ADC channels 0, 1, and 2 0123 ADC channels 0, 1, 2, and 3 •...
Page 374 Atmel AVR XMEGA AU Table 28-8. ADC event mode select. SWEEP One sweep of all ADC channels defined by SWEEP on incoming event channel with the lowest number defined by EVSEL SYNCSWEEP One sweep of all active ADC channels defined by SWEEP on incoming event channel with the lowest number defined by EVSE.
Page 375 Atmel AVR XMEGA AU • Bit 3:0 – CH[3:0]IF: Interrupt Flags These flags are set when the ADC conversion is complete for the corresponding ADC channel. If an ADC channel is configured for compare mode, the corresponding flag will be set if the com- pare condition is met.
Page 376 Atmel AVR XMEGA AU 28.16.10 CHnRESH – Channel n Result Register High The CHnRESL and CHnRESH register pair represents the 16-bit value, CHnRES. For details on reading 16-bit registers, refer to ”Accessing 16-bit Registers” on page 12-bit, left CHRES[11:4] 12-bit, right –...
Page 377: Register Description - Adc Channel
Atmel AVR XMEGA AU • Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 28.16.12 CMPH – Compare Register High The CMPH and CMPL register pair represents the 16-bit value, CMP.
Page 378 Atmel AVR XMEGA AU Table 28-8 on page 373. Gain is valid only with certain MUX settings. See ”MUXCTRL – ADC Channel MUX Control registers” on page 378. Table 28-10. ADC gain factor. GAIN[2:0] Group Configuration Gain Factor DIV2 ½x •...
Page 379 Atmel AVR XMEGA AU • Bit 6:3 – MUXPOS[3:0]: MUX Selection on Positive ADC Input These bits define the MUX selection for the positive ADC input. Table 28-13 on page 379 Table 28-14 on page 379 show the possible input selection for the different input modes.
Page 380 Atmel AVR XMEGA AU Table 28-15. ADC MUXPOS configuration when INPUTMODE[1:0] = 11 (differential with gain) is used. (Continued) 0100 PIN4 ADC4 pin 0101 PIN5 ADC5 pin 0110 PIN6 ADC6 pin 0111 PIN7 ADC7 pin 1XXX Reserved Depending on the device pin count and feature configuration, the actual number of analog input pins may be less than 16.
Page 381 Atmel AVR XMEGA AU 28.17.3 INTCTRL – Channel Interrupt Control registers +0x02 – – – – INTMODE[1:0} INTLVL[1:0] INTCTRL Read/Write Initial Value • Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 382 Atmel AVR XMEGA AU The RESL and RESH register pair represents the 16-bit value, ADCRESULT. Reading and writ- ing 16-bit values require special attention. Refer to ”Accessing 16-bit Registers” on page 13 details. 12-bit, left. RES[11:4] 12-bit, right +0x05 –...
Page 383 Atmel AVR XMEGA AU • Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 28.17.7 SCAN – Channel Scan register Scan is enabled when COUNT is set differently than 0.
Page 384: Register Summary - Adc
Atmel AVR XMEGA AU 28.18 Register Summary – ADC This is the register summary when the ADC is configured to give standard 12-bit results. The register summaries for 8-bit and 12-bit left adjusted will be similar, but with some changes in the result registers, CHnRESH and CHnRESL.
Page 385: Interrupt Vector Summary
Atmel AVR XMEGA AU 28.20 Interrupt vector Summary Table 28-19. Analog-to-digital converter interrupt vectors and their word offset address. Offset Source Interrupt Description 0x00 Analog-to-digital converter channel 0 interrupt vector 0x02 Analog-to-digital converter channel 1 interrupt vector 0x04 Analog-to-digital converter channel 2 interrupt vector...
Page 386: Dac - Digital To Analog Converter
Atmel AVR XMEGA AU 29. DAC – Digital to Analog Converter 29.1 Features • 12-bit resolution • Two independent, continuous-drive output channels • Up to one million samples per second conversion rate per DAC channel • Built-in calibration that removes: –...
Page 387: Voltage Reference Selection
Atmel AVR XMEGA AU A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
Page 388: Dac Clock
Atmel AVR XMEGA AU Figure 29-2. DAC output model feedback DAC voltage DAC out Buffer DAC output channel 29.7 DAC clock The DAC is clocked directly from the peripheral clock (clk ), and this puts a limitation on how fast new data can be clocked into the DAC data registers.
Page 389 Atmel AVR XMEGA AU Equation 29-3.Gain calibration. GCAL 6 [ ] GCAL 5 [ ] GCAL 4 [ ] GCAL 3 [ ] GCAL 2 [ ] GCAL 1 [ ] GCAL 0 [ ] ⎛ ⎞ ⎞ ⎛ ⎞...
Page 390: Register Description
Atmel AVR XMEGA AU 29.10 Register Description 29.10.1 CTRLA – Control Register A +0x00 – – – IDOEN CH1EN CH0EN LPMODE ENABLE CTRLA Read/Write Initial Value • Bit 7:5 – Reserved These bite are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 391 Atmel AVR XMEGA AU Table 29-1. DAC channel selection CHSEL[1:0] Group Configuration Description SINGLE Single-channel operation on channel 0 SINGLE1 Single-channel operation on channel 1 DUAL Dual-channel operation – Reserved • Bit 4:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 392 Atmel AVR XMEGA AU • Bit 0 - LEFTADJ: Left-Adjust Value If this bit is set, CH0DATA and CH1DATA are left-adjusted. 29.10.4 EVCTRL – Event Control Register +0x03 – – – – EVSEL[3:0] EVCTRL Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use.
Page 393 Atmel AVR XMEGA AU • Bit 1 – CH1DRE: Channel 1 Data Register Empty This bit when set indicates that the data register for channel 1 is empty, meaning that a new con- version value may be written. Writing to the data register when this bit is cleared will cause the pending conversion data to be overwritten.
Page 394 Atmel AVR XMEGA AU 29.10.7 CH0DATAL – Channel 0 Data Register Low Right-adjust CHDATA[7:0] +0x18 Left-adjust CHDATA[3:0] – – – – Right-adjust Read/Write Left-adjust Read/Write Right-adjust Initial Value Left-adjust Initial Value 29.10.7.1 Right-adjusted • Bit 7:0 – CHDATA[7:0]: Conversion Data Register Channel 0, Eight lsbs These bits are the eight lsbs of the 12-bit value to convert to channel 0 in right-adjusted mode.
Page 395 Atmel AVR XMEGA AU 29.10.9 CH1DATAL – Channel 1 Data Register Low Right-adjust CHDATA[7:0] +0x1A Left-adjust CHDATA[3:0] – – – – Right-adjust Read/Write Left-adjust Read/Write Right-adjust Initial Value Left-adjust Initial Value 29.10.9.1 Right-adjusted • Bit 7:0 – CHDATA[7:0]: Conversion Data Register Channel 1, Eight lsbs These bits are the eight lsbs of the 12-bit value to convert to channel 1 in right-adjusted mode.
Page 396 Atmel AVR XMEGA AU 29.10.12 CH1GAINCAL – Gain Calibration Register +0x0A CH1GAINCAL[7:0] CH1GAINCAL Read/Write Initial Value • Bit 7:0 – CH0GAINCAL[7:0]: Gain Calibration value These bits are used to compensate for the gain error in DAC channel 1. See ”Calibration” on page 388 for details.
Page 397: Register Summary
Atmel AVR XMEGA AU 29.11 Register Summary This is the I/O summary when the DAC is configured to give standard 12-bit results. The I/O summary for 12-bit left-adjusted results will be similar, but with some changes in the CHnDATAL and CHnDATAH data registers.
Page 398: Ac - Analog Comparator
Atmel AVR XMEGA AU 30. AC – Analog Comparator 30.1 Features • Selectable propagation delay versus current consumption • Selectable hysteresis – None – Small – Large • Analog comparator output available on pin • Flexible input selection – All pins on the port –...
Page 399: Input Sources
Atmel AVR XMEGA AU Figure 30-1. Analog comparator overview. Pin Input AC0OUT Pin Input Hysteresis Enable Interrupts Interrupt Interrupt Sensititivity Mode Voltage Control ACnMUXCTRL ACnCTRL WINCTRL Scaler & Window Events Function Enable Bandgap Hysteresis Pin Input AC1OUT Pin Input 30.3 Input Sources Each analog comparator has one positive and one negative input.
Page 400: Window Mode
Atmel AVR XMEGA AU (falling edge). Events are generated at all times for the same condition as the interrupt, regard- less of whether the interrupt is enabled or not. 30.6 Window Mode Two analog comparators on the same port can be configured to work together in window mode.
Page 401: Register Description
Atmel AVR XMEGA AU 30.9 Register Description 30.9.1 ACnCTRL – Analog Comparator n Control register +0x00 / +0x01 INTMODE[1:0] INTLVL[1:0] HSMODE HYSMODE[2:0] ENABLE ACnCTRL Read/Write Initial Value • Bit 7:6 – INTMODE[1:0]: Interrupt Modes These bits configure the interrupt mode for analog comparator n according to Table 30-1.
Page 402 Atmel AVR XMEGA AU 30.9.2 ACnMUXCTRL – Analog Comparator n Mux Control register – +0x02 / +0x03 – MUXPOS[2:0] MUXNEG[2:0] ACnMUXCTRL Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 403 Atmel AVR XMEGA AU 30.9.3 CTRLA – Control register A +0x04 – – – – – – AC1OUT AC0OUT CTRLA Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 404 Atmel AVR XMEGA AU • Bits 3:2 – WINTMODE[1:0]: Window Interrupt Mode Settings These bits configure the interrupt mode for the analog comparator window mode according to Table 30-5. Table 30-5. Window mode interrupt settings. WINTMODE[1:0] Group Configuration Description ABOVE...
Page 405 Atmel AVR XMEGA AU This flag is automatically cleared when the analog comparator window interrupt vector is exe- cuted. The flag can also be cleared by writing a one to its bit location. • Bit 1 – AC1IF: Analog Comparator 1 Interrupt Flag This is the interrupt flag for AC1.
Page 406 Atmel AVR XMEGA AU • Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:0 – CALIB[3:0]: Current Source Calibration The constant current source is calibrated during production.
Page 407: Register Summary
Atmel AVR XMEGA AU 30.10 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 AC0CTRL INTMODE[1:0] INTLVL[1:0] HSMODE HYSMODE[1:0] ENABLE +0x01 AC1CTRL INTMODE[1:0] INTLVL[1:0] HSMODE HYSMODE[1:0] ENABLE...
Page 408: Ieee 1149.1 Jtag Boundary Scan Interface
Atmel AVR XMEGA AU 31. IEEE 1149.1 JTAG Boundary Scan Interface 31.1 Features • JTAG (IEEE Std. 1149.1-2001 compliant) interface • Boundary scan capabilities according to the JTAG standard • Full scan of all I/O pins • Supports the mandatory SAMPLE, IDCODE, PRELOAD, EXTEST, and BYPASS instructions •...
Page 409 Atmel AVR XMEGA AU • TDI: Test data in. Serial input data to be shifted in to the instruction register or data register (scan chains) • TDO: Test data out. Serial output data from the instruction register or data register The IEEE Std.
Page 410: Jtag Instructions
Atmel AVR XMEGA AU TDO pin. The JTAG instruction selects a particular data register as the path between TDI and TDO and controls the circuitry surrounding the selected data register • Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. The instruction is latched onto the parallel output from the shift register path in the update IR state.
Page 411 Atmel AVR XMEGA AU The active states are: • Capture DR: Data in the IDCODE register are sampled into the device identification register • Shift DR: The IDCODE scan chain is shifted by the TCK input 31.4.3 SAMPLE/PRELOAD; 0x2 SAMPLE/PRELOAD is the instruction for preloading the output latches and taking a snapshot of the input/output pins without affecting system operation.
Page 412: Boundary Scan Chain
Atmel AVR XMEGA AU The active states are: • Capture DR: Parallel data from the PDI are sampled into the PDICOM data register • Shift DR: The PDICOM data register is shifted by the TCK input • Update DR: Commands or operands are parallel-latched from the PDICOM data register into the PDI 31.5...
Page 413: Data Registers
Atmel AVR XMEGA AU 31.5.2 Scanning the PDI Pins Two observe-only cells are inserted to make the combined RESET and PDI_CLK pin and the PDI_DATA pin observable. Even though the PDI_DATA pin is bidirectional, it is only made observable in order to avoid any extra logic on the PDI_DATA output path.
Page 414 The part number is a 16-bit code identifying the device. Refer to the device data sheets to find the correct number. 31.6.2.3 Manufacturer ID The manufacturer ID is an 11-bit code identifying the manufacturer. For Atmel, this code is 0x01F. 31.6.3 Boundary Scan Chain The boundary scan chain has the capability of driving and observing the logic levels on all I/O pins.
Page 415: Program And Debug Interface
It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level.
Page 416: Pdi Physical
Figure 32-2 on page 416 shows a typical connection. Figure 32-2. PDI connection. PDI_CLK PDI_DATA Connector The remainder of this section is intended for use only by third parties developing programmers or programming support for Atmel AVR XMEGA devices. 8331B–AVR–03/12...
Page 417 Atmel AVR XMEGA AU 32.3.1 Enabling The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width data). This will disable the RESET functionality of the Reset pin, if not already disabled by the fuse settings.
Page 418 Atmel AVR XMEGA AU Three different characters are used, DATA, BREAK, and IDLE. The BREAK character is equal to a 12-bit length of low level. The IDLE character is equal to a 12- bit length of high level. The BREAK and IDLE characters can be extended beyond the 12-bit length.
Page 419 Atmel AVR XMEGA AU 32.3.6 Serial Reception When a start bit is detected, the receiver starts to collect the eight data bits. If the parity bit does not correspond to the parity of the data bits, a parity error has occurred. If one or both of the stop bits are low, a frame error has occurred.
Page 420: Jtag Physical
Atmel AVR XMEGA AU Figure 32-8. Driving data out on the PDI_DATA using a bus keeper. PDI_CLK Output enable PDI Output PDI_DATA If the programmer and the PDI both drive the PDI_DATA line at the same time, drive contention will occur, as illustrated in Figure 32-9 on page 420.
Page 421 JTAG disable bit in the MCU control register from the application code. 32.4.3 JTAG Instruction Set The Atmel XMEGA specific JTAG instruction set consist of eight instructions related to boundary scan and PDI access for programming. For more details on JTAG and the general JTAG instruc- tion set, refer to ”JTAG Instructions”...
Page 422 Atmel AVR XMEGA AU Figure 32-11. Special data characters. 1 BREAK CHARACTER (BB+P1) 1 DELAY CHARACTER (DB+P1) 1 EMPTY CHARACTER (EB+P1) 32.4.5 Serial transmission and reception The JTAG interface supports full-duplex communication. At the same time as input data is shifted in on the TDI pin, output data is shifted out on the TDO pin.
Page 423: Pdi Controller
Atmel AVR XMEGA AU If the PDI is in TX- mode (as a response to an LD instruction), but no transmission request from the PDI controller is pending when the TAP controller enters the capture DR state, a DELAY byte (0xDB) will be loaded into the shift register, and the parity bit will be set (forcing a parity error) when data is shifted out in the shift DR state.
Page 424 Atmel AVR XMEGA AU 32.5.1 Switching between PDI and JTAG modes The PDI controller uses either the JTAG or PDI physical layer for establishing a connection to the programmer. Based on this, the PDI is in either JTAG or PDI mode. When one of the modes is entered, the PDI controller registers will be initialized, and the correct clock source will be selected.
Page 425 Atmel AVR XMEGA AU Due to this mechanism, the programmer can always synchronize the protocol by transmitting two successive BREAK characters. 32.5.5 Reset Signalling Through the reset register, the programmer can issue a reset and force the device into reset.
Page 426 Atmel AVR XMEGA AU address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). Multiple-bytes access is internally broken down to repeated single-byte accesses, but it reduces the protocol overhead. 32.5.6.5...
Page 427: Register Description - Pdi Instruction And Addressing Registers
Atmel AVR XMEGA AU Figure 32-14. PDI instruction set summary. Size A Size B LDCS (LDS Control/Status) REPEAT STCS (STS Control/Status) Size A/B Size A - Address size (direct access) Byte Word (2 Bytes) 3 Bytes Long (4 Bytes) CS Address...
Page 428 Atmel AVR XMEGA AU addressing is based on an address already stored in the pointer register prior to the access itself. Indirect data access can be optionally combined with pointer register post-increment. The indirect access mode has an option that makes it possible to load or read the pointer register without accessing any other registers.
Page 429: Register Description - Pdi Control And Status Registers
Atmel AVR XMEGA AU 32.7 Register Description – PDI Control and Status Registers The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI itself.
Page 430: Register Summary
Atmel AVR XMEGA AU – • Bit 2:0 GUARDTIME[2:0]: Guard Time These bits specify the number of IDLE bits of guard time that are inserted in between PDI recep- tion and transmission direction changes. The default guard time is 128 IDLE bits, and the...
Page 431: Memory Programming
33.2 Overview This section describes how to program the nonvolatile memory (NVM) in Atmel AVR XMEGA devices, and covers both self-programming and external programming. The NVM consists of the flash program memory, user signature and calibration rows, fuses and lock bits, and EEPROM data memory.
Page 432: Nvm Controller
Atmel AVR XMEGA AU The device can be locked to prevent reading and/or writing of the NVM. There are separate lock bits for external programming access and self-programming access to the boot loader section, application section, and application table section.
Page 433: Flash And Eeprom Page Buffers
Atmel AVR XMEGA AU This ensures that the given command is executed and the operations finished before the start of a new operation. The external programmer or application software must ensure that the NVM is not addressed when it is busy with a programming operation.
Page 434: Flash And Eeprom Programming Sequences
Atmel AVR XMEGA AU selected page buffer location to tag them. When performing an EEPROM page erase, the actual value of the tagged location does not matter. The EEPROM page buffer is automatically erased after: • A system reset • Executing the write EEPROM page command •...
Page 435: Protection Of Nvm
Atmel AVR XMEGA AU Alternative 1: • Fill the EEPROM page buffer with the selected number of bytes • Perform a EEPROM page erase • Perform a EEPROM page write Alternative 2: • Fill the EEPROM page buffer with the selected number of bytes •...
Page 436 Atmel AVR XMEGA AU out the program memory code. It has the capability to write into the entire flash, including the boot loader section. The boot loader can thus modify itself, and it can also erase itself from the flash if the feature is not needed anymore.
Page 437 Atmel AVR XMEGA AU Figure 33-1. Flash addressing for self-programming. Z-Pointer FPAGE FWORD Low/High Byte select for (E)LPM PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE FPAGE PROGRAM MEMORY PAGE FWORD PAGE INSTRUCTION WORD PAGEEND FLASHEND 33.11.2 NVM Flash Commands...
Page 438 Atmel AVR XMEGA AU Table 33-2. Flash self-programming commands (Continued). Data Change Address Registe CMD[6:0] Group Configuration Description Trigger Halted Busy Protected Pointer 0x02E WRITE_FLASH_PAGE Write flash page Z-pointer 0x2F ERASE_WRITE_FLASH_PAGE Erase and write flash page Z-pointer 0x3A FLASH_RANGE_CRC Flash range CRC...
Page 439 Atmel AVR XMEGA AU 33.11.2.3 Load Flash Page Buffer The load flash page buffer command is used to load one word of data into the flash page buffer. 1. Load the NVM CMD register with the load flash page buffer command.
Page 440 Atmel AVR XMEGA AU In order to use the flash range CRC command, all the boot lock bits must be unprogrammed (no locks). The command execution will be aborted if the boot lock bits for an accessed location are set.
Page 441 Atmel AVR XMEGA AU 1. Load the Z-pointer with the flash page to write. The page address must be written to FPAGE. Other bits in the Z-pointer will be ignored during this operation. 2. Load the NVM CMD register with the erase and write application section/boot loader section page command.
Page 442 Atmel AVR XMEGA AU 1. Load the Z-pointer with the byte address to read. 2. Load the NVM CMD register with the read user signature row / calibration row command 3. Execute the LPM instruction. The destination register will be loaded during the execution of the LPM instruction.
Page 443 Atmel AVR XMEGA AU Load the NVM CMD register with the read fuses command. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The result will be available in the NVM DATA0 register. The CPU is halted during the complete execution of the command.
Page 444 Atmel AVR XMEGA AU When EEPROM memory mapping is enabled, loading a data byte into the EEPROM page buffer can be performed through direct or indirect store instructions. Only the least-significant bits of the EEPROM address are used to determine locations within the page buffer, but the complete memory mapped EEPROM address is always required to ensure correct address mapping.
Page 445 Atmel AVR XMEGA AU 33.11.5.2 Erase EEPROM Page Buffer The erase EEPROM page buffer command is used to erase the EEPROM page buffer. 1. Load the NVM CMD register with the erase EEPROM buffer command. 2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming.
Page 446: External Programming
Atmel AVR XMEGA AU The BUSY flag in the NVM STATUS register will be set until the operation is finished. 33.11.5.7 Read EEPROM The read EEPROM command is used to read one byte from the EEPROM. Load the NVM CMD register with the read EEPROM command.
Page 447 Atmel AVR XMEGA AU Figure 33-3. Memory map for PDI accessing the data and program memories. TOP=0x1FFFFFF FLASH_BASE = 0x0800000 EPPROM_BASE = 0x08C0000 FUSE_BASE = 0x08F0020 DATAMEM_BASE = 0x1000000 DATAMEM 16 MB (mapped IO/SRAM) APP_BASE = FLASH_BASE BOOT_BASE = FLASH_BASE + SIZE_APPL...
Page 448 Atmel AVR XMEGA AU data registers, but the NVM controller must be loaded with the correct command (i.e., to read from any NVM, the controller must be loaded with the NVM read command before loading data from the PDIBUS address space). For the reminder of this section, all references to reading and...
Page 449 Atmel AVR XMEGA AU Change CMD[6:0] Commands / Operation Trigger Protected NVM Busy 0x38 Application section CRC CMDEX Boot Loader Section 0x68 Erase boot section PDI write 0x2A Erase boot loader section page PDI write 0x2C Write boot loader section page...
Page 450 Atmel AVR XMEGA AU 1. Load the NVM CMD register with the read NVM command. 2. Read the selected memory address by executing a PDI read operation. Dedicated read EEPROM, read fuse, read signature row, and read calibration row commands are also available for the various memory sections.
Page 451 Atmel AVR XMEGA AU 33.12.3.7 Erase and Write Page The erase and write application section page, erase and write boot loader section page, and erase and write EEPROM page commands are used to erase one page and then write a loaded flash/EEPROM page buffer into that page in the selected memory space in one atomic operation.
Page 452: Register Description
Atmel AVR XMEGA AU 33.13 Register Description Refer to ”Register Description – NVM Controller” on page 26 for a complete register description of the NVM controller. Refer to ”Register Description – PDI Control and Status Registers” on page 429 for a complete register description of the PDI.
Page 453: Peripheral Module Address Map
Atmel AVR XMEGA AU 34. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA. All peripherals and modules are not present in all XMEGA devices, refer to device data sheet for the peripherals module address map for a specific device.
Page 454 Atmel AVR XMEGA AU Base address Name Description Page 0x0380 Analog comparator pair on port A 0x0390 Analog comparator pair on port B 0x0400 Real time counter 0x0420 RTC32 32-bit Real time counter 0x0440 External bus interface 0x0480 TWIC Two wire interface on port C...
Page 455 Atmel AVR XMEGA AU Base address Name Description Page 0x09A0 USARTD0 USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0x09C0 SPID Serial peripheral interface on port D 0x0A00 TCE0 Timer/counter 0 on port E 0x0A40 TCE1...
Page 456: Instruction Set Summary
Atmel AVR XMEGA AU Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ← Rd, Rr Add without Carry Rd + Rr Z,C,N,V,S,H ← Rd, Rr Add with Carry Rd + Rr + C Z,C,N,V,S,H ←...
Page 457 Atmel AVR XMEGA AU Mnemonics Operands Description Operation Flags #Clocks ← RCALL Relative Call Subroutine PC + k + 1 None 2 / 3 ← ICALL Indirect Call to (Z) PC(15:0) None 2 / 3 ← PC(21:16) ← EICALL Extended Indirect Call to (Z)
Page 458 Atmel AVR XMEGA AU Mnemonics Operands Description Operation Flags #Clocks ← MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None ← Rd, K Load Immediate None ← (1)(2) Rd, k Load Direct from data space None ← (1)(2) Rd, X...
Page 459 Atmel AVR XMEGA AU Mnemonics Operands Description Operation Flags #Clocks ← ELPM Rd, Z+ Extended Load Program Memory and Post- (RAMPZ:Z), None ← Increment Z + 1 ← Store Program Memory (RAMPZ:Z) R1:R0 None ← Store Program Memory and Post-Increment...
Page 460 Atmel AVR XMEGA AU Mnemonics Operands Description Operation Flags #Clocks ← Clear Zero Flag ← Global Interrupt Enable ← Global Interrupt Disable ← Set Signed Test Flag ← Clear Signed Test Flag ← Set Two’s Complement Overflow ← Clear Two’s Complement Overflow ←...
Page 461: Appendix A: Ebi Timing Diagrams
Atmel AVR XMEGA AU 36. Appendix A: EBI Timing Diagrams 36.1 SRAM 3-Port ALE1 CS Figure 36-1. Write, no ALE Write, no ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] Figure 36-2. Write, ALE Write, ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8]...
Page 462 Atmel AVR XMEGA AU Figure 36-3. Read, no ALE Read, no ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] Figure 36-4. Read, ALE Read, ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[15:8] A[7:0] 8331B–AVR–03/12...
Page 463: Sram 3-Port Ale12 Cs
Atmel AVR XMEGA AU 36.2 SRAM 3-Port ALE12 CS Figure 36-5. Write, no ALE Write, no ALE PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[7:0] Figure 36-6. Write, ALE1 Write, ALE1 PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[15:8] A[7:0] 8331B–AVR–03/12...
Page 464 Atmel AVR XMEGA AU Figure 36-7. Write, ALE1 + ALE2 Write, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[23:16] A[15:8] A[7:0] Figure 36-8. Read, no ALE Read, no ALE PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[7:0] 8331B–AVR–03/12...
Page 465 Atmel AVR XMEGA AU Figure 36-9. Read, ALE1 Read, ALE1 PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[15:8] A[7:0] Figure 36-10. Read, ALE1 + ALE2 Read, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[23:16] A[15:8] A[7:0] 8331B–AVR–03/12...
Page 466: Sram 4-Port Ale2 Cs
Atmel AVR XMEGA AU 36.3 SRAM 4-Port ALE2 CS Figure 36-11. Write, no ALE Write, no ALE PER2 ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[7:0] A[15:8] A[15:8] Figure 36-12. Write, ALE Write, ALE PER2 ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[23:16] A[7:0] A[15:8] A[15:8]...
Page 467 Atmel AVR XMEGA AU Figure 36-13. Read, no ALE Read, no ALE PER2 ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[7:0] A[15:8] A[15:8] Figure 36-14. Read, ALE Read, ALE PER2 ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[23:16] A[7:0] A[15:8] A[15:8] 8331B–AVR–03/12...
Page 468: Sram 4- Port Noale Cs
Atmel AVR XMEGA AU 36.4 SRAM 4- Port NOALE CS Figure 36-15. Write Write PER2 D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] Figure 36-16. Read Read PER2 D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] 8331B–AVR–03/12...
Page 469: Lpc 2- Port Ale12 Cs
Atmel AVR XMEGA AU 36.5 LPC 2- Port ALE12 CS Figure 36-17. Write, ALE1 Write, ALE1 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-18. Write, ALE1 + ALE2 Write, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[15:8] A[7:0] D[7:0] 8331B–AVR–03/12...
Page 470 Atmel AVR XMEGA AU Figure 36-19. Read, ALE1 Read, ALE1 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-20. Read, ALE1 + ALE2 Read, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[15:8] A[7:0] D[7:0] 8331B–AVR–03/12...
Page 471: Lpc 3- Port Ale1 Cs
Atmel AVR XMEGA AU 36.6 LPC 3- Port ALE1 CS Figure 36-21. Write Write PER2 ALE1 D[7:0]/A[7:0] A[7:0] D[7:0] A[15:8] A[15:8] Figure 36-22. Read Read PER2 ALE1 D[7:0]/A[7:0] A[7:0] D[7:0] A[15:8] A[15:8] 8331B–AVR–03/12...
Page 472: Lpc 2- Port Ale1 Cs
Atmel AVR XMEGA AU 36.7 LPC 2- Port ALE1 CS Figure 36-23. Write Write PER2 ALE1 D[7:0]/A[7:0] A[7:0] D[7:0] Figure 36-24. Read Read PER2 ALE1 D[7:0]/A[7:0] A[7:0] D[7:0] 8331B–AVR–03/12...
Page 473: Sram 3- Port Ale1 No Cs
Atmel AVR XMEGA AU 36.8 SRAM 3- Port ALE1 no CS Figure 36-25. Write, no ALE Write, no ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] A[19:16] A[19:16] Figure 36-26. Write, ALE Write, ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[15:8] A[7:0]...
Page 474 Atmel AVR XMEGA AU Figure 36-27. Read, no ALE Read, no ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] A[19:16] A[19:16] Figure 36-28. Read, ALE Read, ALE PER2 ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[15:8] A[7:0] A[19:16] A[19:16] 8331B–AVR–03/12...
Page 475: Sram 4- Port Noale No Cs
Atmel AVR XMEGA AU 36.9 SRAM 4- Port NOALE no CS Figure 36-29. Write Write PER2 D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] A[21:18] A[21:18] Figure 36-30. Read Read PER2 D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] A[21:18] A[21:18] 8331B–AVR–03/12...
Page 476: Lpc 2- Port Ale12 No Cs
Atmel AVR XMEGA AU 36.10 LPC 2- Port ALE12 no CS Figure 36-31. Write, ALE1 Write, ALE1 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-32. Write, ALE1 + ALE2 Write, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[15:8] A[7:0] D[7:0]...
Page 477 Atmel AVR XMEGA AU Figure 36-33. Read, ALE1 Read, ALE1 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-34. Read, ALE1 + ALE2 Read, ALE1 + ALE2 PER2 ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[15:8] A[7:0] D[7:0] 8331B–AVR–03/12...
Page 478: Sdram Init
Atmel AVR XMEGA AU 36.11 SDRAM init Figure 36-35. SDRAM init PER2 BA[1:0] A[11:0] 0x400 Mode Register * The number of NOPs is equal to RPDLY[2:0] (RPDLY = 1 is shown) ** The Auto Refresh and following NOPs are repeated 8 times The number of NOPs is equal to ROWCYCDLY[2:0] (ROWCYCDLY = 1 is shown) 8331B–AVR–03/12...
Page 479: Sdram 8-Bit Write
Atmel AVR XMEGA AU 36.12 SDRAM 8-bit Write Figure 36-36. Single write Single write PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr 0x400 D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown) ** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown) *** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown) 8331B–AVR–03/12...
Page 480 Atmel AVR XMEGA AU Figure 36-37. Two consecutive writes Two consecutive writes PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 481 Atmel AVR XMEGA AU Figure 36-38. Burst access within a single page Burst access within a single page PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr Col Adr 0x400 Col Adr D[7:0] D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 482 Atmel AVR XMEGA AU Figure 36-39. Burst access crossing page boundary Burst access crossing page boundary PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 Col Adr D[7:0] D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 483: Sdram 8-Bit Read
Atmel AVR XMEGA AU 36.13 SDRAM 8-bit read Figure 36-40. Single read Single read PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr 0x400 D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown) ** NOP is only inserted for CAS3 *** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
Page 484 Atmel AVR XMEGA AU Figure 36-41. Two consecutive reads Two consecutive reads PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 485 Atmel AVR XMEGA AU Figure 36-42. Burst access within a single page Burst access within a single page PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr Col Adr Col Adr 0x400 D[7:0] D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 486 Atmel AVR XMEGA AU Figure 36-43. Burst access crossing page boundary Burst access crossing page boundary PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr Col Adr 0x400 Col Adr 0x400 D[7:0] D[7:0] D[7:0] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 487: Sdram 4-Bit Write
Atmel AVR XMEGA AU 36.14 SDRAM 4-bit write Figure 36-44. Single write Single write PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr 0x400 D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 488 Atmel AVR XMEGA AU Figure 36-45. Two consecutive writes Two consecutive writes PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 D[3:0] D[7:4] D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 489 Atmel AVR XMEGA AU Figure 36-46. Burst access within a single page Burst access within a single page PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr 0x400 Col Adr Col Adr D[3:0] D[7:4] D[3:0] D[7:4] D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 490 Atmel AVR XMEGA AU Figure 36-47. Burst access crossing page boundary Burst access crossing page boundary PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 Col Adr D[3:0] D[7:4] D[3:0] D[7:4] D[3:0]...
Page 491: Sdram 4-Bit Read
Atmel AVR XMEGA AU 36.15 SDRAM 4-bit read Figure 36-48. Single read Single read PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr 0x400 D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 492 Atmel AVR XMEGA AU Figure 36-49. Two consecutive reads Two consecutive reads PER2 BA[1:0] Bank Adr Bank Adr A[11:0] Row Adr Col Adr 0x400 Row Adr Col Adr 0x400 D[3:0] D[7:4] D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 493 Atmel AVR XMEGA AU Figure 36-50. Burst access within a single page Burst access within a single page PER2 BA[1:0] Bank Adr A[11:0] Row Adr Col Adr Col Adr Col Adr 0x400 D[3:0] D[7:4] D[3:0] D[7:4] D[3:0] D[7:4] * The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
Page 494: Sram Refresh
Atmel AVR XMEGA AU 36.16 SRAM refresh Figure 36-52. Autorefresh when idle Autorefresh when idle PER2 BA[1:0] A[11:0] * The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown) ** The number of NOPs is equal to ESRDLY[2:0] (ESRDLY = 1 is shown)
Page 495 Atmel AVR XMEGA AU Figure 36-53. Autorefresh between two accesses Autorefresh between two acesses PER2 BA[1:0] A[11:0] * The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown) ** The number of NOPs is equal to ESRDLY[2:0] (ESRDLY = 1 is shown)
Page 496 Atmel AVR XMEGA AU Figure 36-54. Enter Self Refresh Enter Self Refresh PER2 BA[1:0] A[11:0] * The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown) ** The number of NOPs is equal to ESRDLY[2:0] (ESRDLY = 1 is shown)
Page 497 Atmel AVR XMEGA AU Figure 36-55. Exit Self Refresh Exit Self Refresh PER2 BA[1:0] A[11:0] * The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown) ** The number of NOPs is equal to ESRDLY[2:0] (ESRDLY = 1 is shown)
Page 498: Datasheet Revision History
Atmel AVR XMEGA AU 37. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 37.1 8331B – 03/12 Added Table 2-1 ”XMEGA AU feature summary overview.”...
Page 499 Atmel AVR XMEGA AU Updated ”DATA – Data register” on page 284. Added the description of ADDR[7:1] and ADDR[0]. Updated the formula in ”Fractional Baud Rate Generation” on page 304. Updated Figure 23-9 on page 305, the “Fractional baud rate example.”...
Page 500: Table Of Contents
Atmel AVR XMEGA AU Table Of Contents About the Manual ..................2 Reading the Manual ..................2 Resources ......................2 Recommended Reading ..................2 Overview ....................3 AVR CPU ....................7 Features ......................7 Overview ......................7 Architectural Overview ..................7 ALU - Arithmetic Logic Unit ................8 Program Flow ....................9...
Page 501 Atmel AVR XMEGA AU 4.12 Device ID and Revision ...................25 4.13 JTAG Disable ....................25 4.14 I/O Memory Protection ..................25 4.15 Register Description – NVM Controller ............26 4.16 Register Descriptions – Fuses and Lock bits ..........31 4.17 Register Description – Production Signature Row ..........37 4.18...
Page 502 Atmel AVR XMEGA AU Overview ......................71 Events ......................72 Event Routing Network ..................74 Event Timing ....................76 Filtering ......................76 Quadrature Decoder ..................76 Register Description ..................78 Register Summary ...................82 System Clock and Clock Options ............83 Features ......................83 Overview ......................83 Clock Distribution .....................85 Clock Sources ....................85...
Page 503 Atmel AVR XMEGA AU Features ......................113 Overview ......................113 Reset Sequence ....................114 Reset Sources ....................115 Register Description ..................119 Register Summary ..................120 10 Battery Backup System ............... 121 10.1 Features ......................121 10.2 Overview ......................121 10.3 Battery Backup System .................122 10.4 Configuration ....................123 10.5...
Page 504 Atmel AVR XMEGA AU 13.2 Overview ......................143 13.3 I/O Pin Use and Configuration ...............144 13.4 Reading the Pin Value ...................147 13.5 Input Sense Configuration ................148 13.6 Port Interrupt ....................149 13.7 Port Event ......................150 13.8 Alternate Port Functions ................150 13.9 Slew Rate Control ..................151 13.10...
Page 505 Atmel AVR XMEGA AU 15.2 Overview ......................193 15.3 Block Diagram ....................194 15.4 Clock Sources ....................194 15.5 Counter Operation ..................195 15.6 Compare Channel ..................196 15.7 Interrupts and Events ..................197 15.8 DMA Support ....................198 15.9 Timer/Counter Commands ................198 15.10 Register Description ..................199 15.11...
Page 506 Atmel AVR XMEGA AU 19.4 Register Summary ..................234 19.5 Interrupt Vector Summary ................234 20 USB – Universal Serial Bus Interface ..........235 20.1 Features ......................235 20.2 Overview ......................235 20.3 Operation .......................237 20.4 SRAM Memory Mapping ................240 20.5 Clock Generation ...................241 20.6...
Page 507 Atmel AVR XMEGA AU 21.13 Register Summary - TWI Slave ..............286 21.14 Interrupt Vector Summary ................286 22 SPI – Serial Peripheral Interface ............287 22.1 Features ......................287 22.2 Overview ......................287 22.3 Master Mode ....................288 22.4 Slave Mode ....................288 22.5 Data Modes ....................289 22.6...
Page 508 Atmel AVR XMEGA AU 25 AES and DES Crypto Engines ............320 25.1 Features ......................320 25.2 Overview ......................320 25.3 DES Instruction ....................320 25.4 AES Crypto Module ..................321 25.5 Register Description – AES ................324 25.6 Register Summary - AES ................327 25.7 Interrupt vector Summary - AES ..............327...
Page 509 Atmel AVR XMEGA AU 28.4 ADC Channels ....................360 28.5 Voltage Reference Selection .................361 28.6 Conversion Result ..................361 28.7 Compare Function ..................363 28.8 Starting a Conversion ..................363 28.9 ADC Clock and Conversion Timing ...............363 28.10 ADC Input Model ...................367 28.11 DMA Transfer ....................368 28.12...
Page 510 Atmel AVR XMEGA AU 30.6 Window Mode ....................400 30.7 Input Hysteresis .....................400 30.8 Propagation Delay vs. Power Consumption ..........400 30.9 Register Description ..................401 30.10 Register Summary ..................407 30.11 Interrupt vector Summary ................407 31 IEEE 1149.1 JTAG Boundary Scan Interface ........408 31.1...
Page 511 Atmel AVR XMEGA AU 33.13 Register Description ..................452 33.14 Register Summary ..................452 34 Peripheral Module Address Map ............453 35 Instruction Set Summary ..............456 36 Appendix A: EBI Timing Diagrams ............. 461 36.1 SRAM 3-Port ALE1 CS ..................461 36.2 SRAM 3-Port ALE12 CS ................463...
Page 512 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL...

Atmel AVR XMEGA AU series Manual

1 About the Manual

2 Overview

3 Avr Cpu

4 Memories

5 DMAC - Direct Memory Access Controller

6 Event System

7 System Clock and Clock Options

8 Power Management and Sleep Modes

9 Reset System

10 Battery Backup System

11 WDT - Watchdog Timer

12 Interrupts and Programmable Multilevel Interrupt Controller

13 O Ports

14 TC0/1 - 16-Bit Timer/Counter Type 0 and 1

15 TC2 - 16-Bit Timer/Counter Type 2

16 Awex - Advanced Waveform Extension

17 Hi-Res - High-Resolution Extension

18 RTC - Real-Time Counter

19 RTC32 - 32-Bit Real-Time Counter

20 USB - Universal Serial Bus Interface

21 TWI - Two-Wire Interface

22 SPI - Serial Peripheral Interface

23 Usart

24 IRCOM - IR Communication Module

25 AES and des Crypto Engines

26 CRC - Cyclic Redundancy Check Generator

27 EBI - External Bus Interface

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