Page 1 D microcontroller family. The Atmel AVR XMEGA D is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon- trollers based on the AVR enhanced RISC architecture. The available Atmel AVR XMEGA D modules described in this manual are: •...
Page 2: About The Manual
The possible bit group configurations are listed for all bit groups together with their asso- ciated Group Configuration and a short description. The Group Configuration refers to the defined configuration name used in the Atmel AVR XMEGA D and assembler header files and application note source code.
Page 3: Overview
The Atmel AVR XMEGA D devices are supported with a full suite of program and system devel- opment tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
Page 4: Block Diagram
Atmel AVR XMEGA D Block Diagram Figure 2-1. Atmel AVR XMEGA D block diagram. PR[0..1] PQ[0..7] XTAL1 TOSC1 XTAL2 TOSC2 Oscillator Circuits/ Clock Watchdog Generation Oscillator Real Time Counter EVENT ROUTING NETWORK Watchdog Timer DATA BUS Power Supervision Event System...
Page 5: Avr Cpu
This enables instructions to be executed on every clock cycle. For a summary of all AVR instructions, refer to ”Instruction Set Summary” on page 317. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 3-1. Block diagram of the AVR CPU architecture. 8210C–AVR–09/11...
Page 6: Alu - Arithmetic Logic Unit
Atmel AVR XMEGA D The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation.
Page 7: Program Flow
Atmel AVR XMEGA D 3.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: • Multiplication of unsigned integers •...
Page 8: Status Register
Atmel AVR XMEGA D Figure 3-3 on page 8 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register.
Page 9: Register File
Atmel AVR XMEGA D The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will auto- matically disable interrupts for up to four instructions or until the next I/O memory write.
Page 10: Ramp And Extended Indirect Registers
Atmel AVR XMEGA D Figure 3-5. The X-, Y- and Z-registers Bit (individually) X-register Bit (X-register) Bit (individually) Y-register Bit (Y-register) Bit (individually) Z-register Bit (Z-register) The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-significant byte (MSB). In the different addressing modes, these address registers function as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
Page 11: Accessing 16-Bit Registers
Atmel AVR XMEGA D 3.11 Accessing 16-bit Registers data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus.
Page 12: Fuse Lock
Atmel AVR XMEGA D 3.12.2 Sequence for execution of protected SPM/LPM 1. The application code writes the signature for the execution of protected SPM/LPM to the CCP register. 2. Within four instruction cycles, the application code must execute the appropriate instruction.
Page 13: Register Descriptions
Atmel AVR XMEGA D 3.14 Register Descriptions 3.14.1 CCP – Configuration Change Protection register +0x04 CCP[7:0] Read/Write Initial Value • Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of the protected instruction for a maximum period of four CPU instruc- tion cycles.
Page 14 Atmel AVR XMEGA D or call to addresses below 128KB, this register is not used. This register is not available if the program memory in the device is less than 128KB. +0x0C EIND[7:0] EIND Read/Write Initial Value • Bit 7:0 – EIND[7:0]: Extended Indirect Address bits These bits hold the MSB of the 24-bit address created by EIND and the 16-bit Z-register.
Page 15 Atmel AVR XMEGA D 3.14.6 SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. +0x0F SREG Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for interrupts to be enabled.
Page 16: Register Summary
Atmel AVR XMEGA D 3.15 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 Reserved – – – – – – – – +0x01 Reserved – –...
Page 17: Memories
Atmel AVR XMEGA D 4. Memories Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage –...
Page 18 Atmel AVR XMEGA D All AVR CPU instructions are 16 or 32 bit wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 18.
Page 19: Fuses And Lockbits
Atmel AVR XMEGA D ming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, applica- tion code can be stored here.
Page 20: Internal Sram
Atmel AVR XMEGA D Figure 4-2. Data memory map. Start/End Data Memory Address 0x0000 I/O Memory (Up to 4 KB) 0x1000 EEPROM (Up to 4 KB) 0x2000 Internal SRAM 0xFFFF I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices.
Page 21: Memory Timing
4.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 4.11 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications.
Page 22: Register Description - Nvm Controller
Atmel AVR XMEGA D 4.12 Register Description – NVM Controller – 4.12.1 ADDR0 Address register 0 The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value ADDR. This is used for addressing all NVM sections for read, write, and CRC operations.
Page 23 Atmel AVR XMEGA D 4.12.5 DATA1 – Data register 1 +0x05 DATA[15:8] DATA1 Read/Write Initial Value • Bit 7:0 – DATA[15:8]: Data Register Byte 1 This register gives the data value byte 1 when accessing NVM locations. 4.12.6 DATA2 – Data register 2...
Page 24 Atmel AVR XMEGA D • Bit 0 – CMDEX: Command Execute Setting this bit will execute the command in the CMD register. This bit is protected by the config- uration change protection (CCP) mechanism. Refer to ”Configuration Change Protection” on page 11 for details on the CCP.
Page 25 Atmel AVR XMEGA D • Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level These bits enable the interrupt and select the interrupt level, as described in ”Interrupts and Pro- grammable Multilevel Interrupt Controller” on page 101. This is a level interrupt that will be triggered when the BUSY flag in the STATUS is set to zero.
Page 26 Atmel AVR XMEGA D 4.12.12 LOCKBITS – Lock Bit register +0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] LOCKBITS Read/Write Initial Value This register is a mapping of the NVM lockbits into the I/O memory space, enable direct read access from the application software. Refer to ”LOCKBITS –...
Page 27: Register Descriptions - Fuses And Lockbits
Atmel AVR XMEGA D 4.13 Register Descriptions – Fuses and Lockbits 4.13.1 FUSEBYTE1 – Fuse Byte1 +0x01 WDWPER[3:0] WDPER[3:0] FUSEBYTE1 Read/Write Initial Value • Bit 7:4 – WDWPER[3:0]: Watchdog Window Timeout Period These fuse bits are used to set initial value of the closed window for the Watchdog Timer in Win- dow Mode.
Page 28 Atmel AVR XMEGA D Table 4-2. TOSCSEL fuse. TOSCSEL Group Configuration Description ALTERNATE TOSC1/2 on separate pins XTAL TOSC1/2 shared with XTAL Note: 1. See device datasheet for alternate TOSC position. • Bit 4:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to one when this register is written.
Page 29 Atmel AVR XMEGA D Table 4-4. Start-up time. STARTUPTIME[1:0] 1kHz ULP Oscillator Cycles Reserved • Bit 1 – WDLOCK: Watchdog Timer Lock The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this fuse is programmed the watchdog timer configuration cannot be changed, and the ENABLE bit in the watchdog CTRL register is automatically set at reset and cannot be cleared from the appli- cation software.
Page 30 Atmel AVR XMEGA D • Bit 3 – EESAVE: EEPROM is Preserved through the Chip Erase A chip erase command will normally erase the flash, EEPROM and internal SRAM. If this fuse is programmed, the EEPROM is not erased during chip erase. This is useful if EEPROM is used to store data independent of software revision.
Page 31 Atmel AVR XMEGA D Table 4-8. Boot lock bit for the boot loader section. BLBB[1:0] Group Configuration Description No lock – no restrictions for SPM and (E)LPM accessing NOLOCK the boot loader section. Write lock – SPM is not allowed to write the boot loader WLOCK section.
Page 32 Atmel AVR XMEGA D • Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section These lock bits control the security level for the application table section. The BLBAT bits can only be written to a more strict locking. Resetting the BLBAT bits is possible by executing a chip erase command.
Page 33: Register Description - Production Signature Row
Atmel AVR XMEGA D 4.14 Register Description – Production Signature Row 4.14.1 RCOSC2M – Internal 2MHz Oscillator Calibration register +0x00 RCOSC2M[7:0] RCOSC2M Read/Write Initial Value • Bit 7:0 – RCOSC2M[7:0]: Internal 2MHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 2MHz oscillator. Calibration of the oscillator is performed during production test of the device.
Page 34 Atmel AVR XMEGA D 4.14.4 RCOSC32M – Internal 32MHz Oscillator Calibration register +0x03 RCOSC32M[7:0] RCOSC32M Read/Write Initial Value • Bit 7:0 – RCOSC32M[7:0]: Internal 32MHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is performed during production test of the device.
Page 35 Atmel AVR XMEGA D • Bit 7:0 – LOTNUM1[7:0]: Lot Number Byte 1 This byte contains byte 1 of the lot number for the device. 4.14.8 LOTNUM2 – Lot Number Register 2 +0x0A LOTNUM2[7:0] LOTNUM2 Read/Write Initial Value • Bit 7:0 – LOTNUM2[7:0]: Lot Number Byte 2 This byte contains byte 2 of the lot number for the device.
Page 36 Atmel AVR XMEGA D 4.14.12 WAFNUM – Wafer Number register +0x10 WAFNUM[7:0] WAFNUM Read/Write Initial Value • Bit 7:0 – WAFNUM[7:0]: Wafer Number This byte contains the wafer number for each device. Together with the lot number and wafer coordinates this gives a serial number for the device.
Page 37 Atmel AVR XMEGA D 4.14.16 COORDY1 – Wafer Coordinate Y register 1 +0x15 COORDY1[7:0] COORDY1 Read/Write Initial Value • Bit 7:0 – COORDY1[7:0]: Wafer Coordinate Y Byte 1 This byte contains byte 1 of wafer coordinate Y for the device.
Page 38 Atmel AVR XMEGA D 4.14.20 ADCBCAL1 – ADCB Calibration register 1 +0x25 ADCBCAL1[7:0] ADCBCAL1 Read/Write Initial Value • Bit 7:0 – ADCBCAL0[7:0]: ADCB Calibration Byte 1 This byte contains byte 1 of the ADCB calibration data, and must be loaded into the ADCB CALH register.
Page 39: Register Description - General Purpose I/O Memory
Atmel AVR XMEGA D 4.15 Register Description – General Purpose I/O Memory 4.15.1 GPIORn – General Purpose I/O register n GPIORn[7:0] GPIORn Read/Write Initial Value These are general purpose register that can be used to store data such as global variables and flags in the bit-accessible I/O memory space.
Page 40 Atmel AVR XMEGA D 4.16.4 REVID – Revision ID +0x03 – – – – REVID[3:0] REVID Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. • Bit 3:0 – REVID[3:0]: Revision ID These bits contains the device revision.
Page 41 Atmel AVR XMEGA D • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 0 – EVSYS0LOCK: Setting this bit will lock all registers in the event system related to event channels 0 to 3 for fur- ther modification.
Page 42: Register Summary - Nvm Controller
Atmel AVR XMEGA D 4.17 Register Summary - NVM Controller Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 ADDR0 Address Byte 0 +0x01 ADDR1 Address Byte 1 +0x02...
Page 43: Register Summary - Production Signature Row
Atmel AVR XMEGA D 4.19 Register Summary - Production Signature Row Address Auto Load Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 RCOSC2M RCOSC2M[7:0] +0x01 RCOSC2MA RCOSC2MA[7:0] +0x02 RCOSC32K...
Page 44: Register Summary - General Purpose I/O Registers
Atmel AVR XMEGA D 4.20 Register Summary - General Purpose I/O Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 GPIOR0 GPIOR[7:0] +0x01 GPIOR1 GPIOR[7:0] +0x02 GPIOR2 GPIOR[7:0]...
Page 45: Event System
Atmel AVR XMEGA D 5. Event System Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU independent operation – 100% predictable signal timing – Short and guaranteed response time •...
Page 46: Events
Atmel AVR XMEGA D Figure 5-1. Event system overview and connected peripherals. CPU / Software Event Routing Network Prescaler Event Real Time System Counter Controller Timer / Counters Port pins IRCOM The event routing network consists of eight software-configurable multiplexers that control how events are routed and used.
Page 47 Atmel AVR XMEGA D Figure 5-2. Example of event source, generator, user, and action. Event Generator Event User Timer/Counter Compare Match Channel Sweep Event Routing Over-/Underflow Single Network Conversion Error Event Action Selection Event Source Event Action Events can also be generated manually in software.
Page 48: Event Routing Network
Atmel AVR XMEGA D Software-generated events last for one clock cycle and will overwrite events from other event generators on that event channel during that clock cycle. Table 5-1 on page 48 shows the different events, how they can be manually generated, and how they are decoded.
Page 49 Atmel AVR XMEGA D Figure 5-3. Event routing network. Event Channel 3 Event Channel 2 Event Channel 1 Event Channel 0 (10) TCC0 TCC1 CH0CTRL[7:0] CH0MUX[7:0] TCD0 TCE0 CH1CTRL[7:0] TCF0 CH1MUX[7:0] (25) ADCA CH2CTRL[7:0] CH2MUX[7:0] (16) (48) PORTA PORTB CH3CTRL[7:0]...
Page 50: Event Timing
Atmel AVR XMEGA D Event Timing An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise stated, an event lasts for one peripheral clock cycle.
Page 51 Atmel AVR XMEGA D Figure 5-4. Quadrature signals from a rotary encoder. 1 cycle / 4 states Forward Direction QDPH0 QDPH90 QDINDX Backward Direction QDPH0 QDPH90 QDINDX Figure 5-4 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the two quadrature signals.
Page 52 Atmel AVR XMEGA D • Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder. • Enable the timer/counter without clock prescaling. The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the timer/counter count register.
Page 53: Register Description
Atmel AVR XMEGA D Register Description 5.8.1 CHnMUX – Event Channel n Multiplexer register CHnMUX[7:0] CHnMUX Read/Write Initial Value • Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer These bits select the event source according to Table 5-3. This table is valid for all XMEGA devices regardless of whether the peripheral is present or not.
Page 54 Atmel AVR XMEGA D Table 5-3. CHnMUX[7:0] bit settings. CHnMUX[7:4] CHnMUX[3:0] Group Configuration Event Source 0100 (Reserved) 0101 PORTA_PINn PORTA pin n (n= 0, 1, 2 ... or 7) 0101 PORTB_PINn PORTB pin n (n= 0, 1, 2 ... or 7)
Page 55 Atmel AVR XMEGA D Table 5-4. QDIRM bit settings. QDIRM[1:0] Index Recognition State {QDPH0, QDPH90} = 0b00 {QDPH0, QDPH90} = 0b01 {QDPH0, QDPH90} = 0b10 {QDPH0, QDPH90} = 0b11 • Bit 4 – QDIEN: Quadrature Decode Index Enable When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be enabled.
Page 56 Atmel AVR XMEGA D 5.8.4 DATA – Data register This register contains the data value when manually generating a data event. This register must be written before the STROBE register. For details, See ”STROBE – Strobe register” on page +0x11...
Page 57: Register Summary
Atmel AVR XMEGA D Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CH0MUX CH0MUX[7:0] +0x01 CH1MUX CH1MUX[7:0] +0x02 CH2MUX CH2MUX[7:0] +0x03 CH3MUX CH3MUX[7:0] +0x04 Reserved –...
Page 58: System Clock And Clock Options
Atmel AVR XMEGA D 6. System Clock and Clock Options Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output •...
Page 59 Atmel AVR XMEGA D Figure 6-1. The clock system, clock sources, and clock distribution. Real Time Non-Volatile Peripherals AVR CPU Counter Memory PER2 PER4 System Clock Prescalers Brown-out Watchdog Detector Timer System Clock Multiplexer (SCLKSEL) RTCSRC PLLSRC XOSCSEL 32 kHz 32.768 kHz...
Page 60: Clock Distribution
Atmel AVR XMEGA D Clock Distribution Figure 6-1 on page 59 presents the principal clock distribution system used in XMEGA devices. 6.3.1 System Clock - Clk The system clock is the output from the main system clock selection. This is fed into the prescal- ers that are used to generate all internal clocks except the asynchronous and USB clocks.
Page 61 Atmel AVR XMEGA D 6.4.1.3 32MHz Run-time Calibrated Oscillator The 32MHz run-time calibrated internal oscillator is a high-requency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital fre- quency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
Page 62: System Clock Selection And Prescalers
Atmel AVR XMEGA D Figure 6-3. External clock drive configuration. General Purpose XTAL2 External Clock XTAL1 Signal 6.4.2.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in...
Page 63: Pll With 1X-31X Multiplication Factor
Atmel AVR XMEGA D Figure 6-5. System clock selection and prescalers. Clock Selection Internal 32.768kHz Osc. PER4 PER2 Internal 2MHz Osc. Internal 32MHz Osc. Prescaler A Prescaler B Prescaler C 1, 2, 4, ... , 512 1, 2, 4 1, 2 Internal PLL.
Page 64: Dfll 2Mhz And Dfll 32Mhz
Atmel AVR XMEGA D DFLL 2MHz and DFLL 32MHz Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to do automatic run-time calibration of the oscillator and compensate for temperature and voltage drift.
Page 65: Pll And External Clock Source Failure Monitor
Atmel AVR XMEGA D COMP = RCOSC RCnCREF When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to adjust the oscillator frequency.
Page 66 Atmel AVR XMEGA D failure monitor is meant for external clock sources above 32kHz. It cannot be used for slower external clocks. When the failure monitor is enabled, it will not be disabled until the next reset. The failure monitor is stopped in all sleep modes where the PLL or external clock source are stopped.
Page 67: Register Description - Clock
Atmel AVR XMEGA D Register Description - Clock 6.9.1 CTRL – Control register +0x00 – – – – – SCLKSEL[2:0] CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 68 Atmel AVR XMEGA D • Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to Table 6-2. These bits can be written at run-time to change the frequency of the Clk...
Page 69 Atmel AVR XMEGA D 6.9.3 LOCK – Lock register +0x02 – – – – – – – LOCK LOCK Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 70: Register Description - Oscillator
Atmel AVR XMEGA D • Bit 0 – RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected RTC clock source for the real-time counter. 6.10 Register Description — Oscillator 6.10.1 CTRL – Oscillator Control register +0x00 –...
Page 71 Atmel AVR XMEGA D 6.10.2 STATUS – Oscillator Status register +0x01 – – – PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY STATUS Read/Write Initial Value • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 72 Atmel AVR XMEGA D Table 6-5. 16MHz crystal oscillator frequency range selection. Typical Frequency Recommended Range for FRQRANGE[1:0] Group Configuration Range Capacitors C1 and C2 (pF) 04TO2 0.4MHz - 2MHz 100-300 2TO9 2MHz - 9MHz 10-40 9TO12 9MHz - 12MHz...
Page 73 Atmel AVR XMEGA D 6.10.4 XOSCFAIL – XOSC Failure Detection register +0x03 – – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN XOSCFAIL Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 74 Atmel AVR XMEGA D 6.10.6 PLLCTRL – PLL Control register +0x05 PLLSRC[1:0] PLLDIV PLLFAC[4:0] PLLCTRL Read/Write Initial Value • Bit 7:6 – PLLSRC[1:0]: Clock Source The PLLSRC bits select the input source for the PLL according to Table 6-7 on page Table 6-7.
Page 75: Register Description - Dfll32M/Dfll2M
Atmel AVR XMEGA D Table 6-8. 32MHz oscillator reference selection. RC32MCREF[1:0] Group Configuration Description RC32K 32.768kHz internal oscillator XOSC32 32.768kHz crystal oscillator on TOSC — Reserved — Reserved • Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference This bit is used to select the calibration source for the 2MHz DFLL. By default, this bit is zero and the 32.768kHz internal oscillator is selected.
Page 76 Atmel AVR XMEGA D • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6:0 – CALA[6:0]: DFLL Calibration Bits These bits hold the part of the oscillator calibration value that is used for automatic runtime cali- bration.
Page 77 Atmel AVR XMEGA D 6.11.5 COMP2 – DFLL Compare register 2 +0x06 COMP[15:8] COMP2 Read/Write Initial Value • Bit 7:0 – COMP2[15:8]: Compare Register Byte 2 These bits hold byte 2 of the 16-bit compare register. Table 6-9. Nominal DFLL32M COMP values for different output frequencies.
Page 78: Register Summary - Clock
Atmel AVR XMEGA D 6.12 Register Summary - Clock Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – SCLKSEL[2:0] +0x01 PSCTRL – PSADIV[4:0]...
Page 79: Power Management And Sleep Modes
Atmel AVR XMEGA D 7. Power Management and Sleep Modes Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable clock and turn off unused peripherals in active and idle...
Page 80 Atmel AVR XMEGA D Table 7-1 on page 80 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources. Table 7-1. Active clock domains and wake-up sources in the different sleep modes. Active Clock Domain Oscillators...
Page 81: Power Reduction Registers
Atmel AVR XMEGA D 7.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
Page 82 Atmel AVR XMEGA D 7.5.4 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and, hence, always consume power.
Page 83: Register Description - Sleep
Atmel AVR XMEGA D Register Description – Sleep 7.6.1 CTRL – Control register +0x00 – – – – SMODE[2:0] CTRL Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 84 Atmel AVR XMEGA D • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 2 – RTC: Real-Time Counter Setting this bit stops the clock to the real-time counter.
Page 85 Atmel AVR XMEGA D 7.7.3 PRPC/D/E/F – Power Reduction Port C/D/E/F register +0x03/+0x04/ – USART1 USART0 HIRES PRPC/D/E/F +0x05/+0x06 Read/Write Initial Value • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Page 86: Register Summary - Sleep
Atmel AVR XMEGA D Register Summary – Sleep Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – SMODE[2:0] Register Summary – Power Reduction Address...
Page 87: Reset System
Atmel AVR XMEGA D 8. Reset System Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset –...
Page 88: Reset Sequence
Atmel AVR XMEGA D Figure 8-1. Reset system overview. MCU Status Register (MCUSR) Power-on Reset Brown-out BODLEVEL [2:0] Reset Pull-up Resistor External SPIKE Reset FILTER Reset Software Reset Watchdog Reset Delay Counters Oscillator TIMEOUT SUT[1:0] Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active.
Page 89: Reset Sources
Atmel AVR XMEGA D Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for Clk 8.3.2 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from the calibration row to the calibration registers.
Page 90 Atmel AVR XMEGA D When the BOD is enabled and V decreases to a value below the trigger level (V Figure BOT- 8-4), the brownout reset is immediately activated. When V increases above the trigger level (V Figure 8-4), the reset counter starts the...
Page 91 Atmel AVR XMEGA D • Enabled: In this mode, the V level is continuously monitored, and a drop in V below V for a period of t will give a brownout reset • Sampled: In this mode, the BOD circuit will sample the V level with a period identical to that of the 1kHz output from the ultra low power (ULP) internal oscillator.
Page 92 Atmel AVR XMEGA D Figure 8-6. Watchdog reset. Cycles 1-2 2MHz For information on configuration and use of the WDT, refer to the ”WDT – Watchdog Timer” on page 8.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the soft- ware reset bit in the reset control register.The reset will be issued within two CPU clock cycles...
Page 93: Register Description
Atmel AVR XMEGA D Register Description 8.5.1 STATUS – Status register +0x00 – – PDIRF WDRF BORF EXTRF PORF STATUS Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 94: Register Summary
Atmel AVR XMEGA D Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 STATUS – – PDIRF WDRF BORF EXTRF PORF +0x01 CTRL – – – –...
Page 95: Wdt - Watchdog Timer
Atmel AVR XMEGA D 9. WDT – Watchdog Timer Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator •...
Page 96: Window Mode Operation
Atmel AVR XMEGA D Figure 9-1. Normal mode operation. Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window time- out period (TO ) and the normal timeout period (TO ). The closed window timeout period WDTW defines a duration of from 8ms to 8s where the WDT cannot be reset.
Page 97: Configuration Protection And Lock
Atmel AVR XMEGA D Configuration Protection and Lock The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings. The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s change enable bit must be written at the same time.
Page 98 Atmel AVR XMEGA D Table 9-1. Watchdog timeout periods (Continued). PER[3:0] Group Configuration Typical Timeout Periods 0110 512CLK 0.512s 0111 1KCLK 1.0s 1000 2KCLK 2.0s 1001 4KCLK 4.0s 1010 8KCLK 8.0s 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved •...
Page 99 Atmel AVR XMEGA D In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by the configuration change protection mechanism. For a detailed description, refer to ”Configuration Change Protection” on page Table 9-2.
Page 100: Register Summary
Atmel AVR XMEGA D • Bit 0 – SYNCBUSY: Synchronization Busy Flag This flag is set after writing to the CTRL or WINCTRL registers and the data are being synchro- nized from the system clock to the WDT clock domain. This bit is automatically cleared after the synchronization is finished.
Page 101: Interrupts And Programmable Multilevel Interrupt Controller
Atmel AVR XMEGA D 10. Interrupts and Programmable Multilevel Interrupt Controller 10.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address –...
Page 102: Operation
Atmel AVR XMEGA D 10.3 Operation Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable ( I ) bit in the CPU status register. The I bit will not be cleared when an interrupt is acknowledged.
Page 103 Atmel AVR XMEGA D 10.4.1 NMI – Non-Maskable Interrupts Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non- maskable interrupts must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
Page 104 Atmel AVR XMEGA D Figure 10-2. Interrupt execution of a multicycle instruction. If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
Page 105: Interrupt Level
Atmel AVR XMEGA D 10.5 Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre- sponding bit values for the interrupt level configuration of all interrupts is shown in Table 10-1.
Page 106 Atmel AVR XMEGA D Figure 10-3. Static priority. Lowes t Addres s IVEC 0 Highes t Priority IVEC x IVEC x+1 Highes t Addres s IVEC N Lowes t Priority 10.6.2 Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts.
Page 107: Interrupt Vector Locations
Atmel AVR XMEGA D 10.7 Interrupt vector locations Table 10-2 on page 107 shows reset and Interrupt vectors placement for the various combina- tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
Page 108 Atmel AVR XMEGA D 10.8.2 INTPRI – Interrupt priority register +0x01 INTPRI[7:0] INTPRI Read/Write Initial Value • Bit 7:0 – INTPRI: Interrupt Priority When round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority the next time one or more low-level interrupts are pending.
Page 109: Register Summary
Atmel AVR XMEGA D • Bit 0 – LOLVLEN: Low-level Interrupt Enable When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt requests will be ignored. Note: 1. Ignoring interrupts will be effective one cycle after the bit is cleared.
Page 110: O Ports
Atmel AVR XMEGA D 11. I/O Ports 11.1 Features • General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O •...
Page 111: I/O Pin Use And Configuration
Atmel AVR XMEGA D Figure 11-1 on page 111 shows the I/O pin functionality and the registers that are available for controlling a pin. Figure 11-1. General I/O pin functionality. Pull Enable Pull Keep PINnCTRL Pull Direction Input Disable Wired AND/OR...
Page 112 Atmel AVR XMEGA D The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin.
Page 113 Atmel AVR XMEGA D 11.3.1.2 Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull- up when set as input. Figure 11-4. I/O pin configuration - Totem-pole with pull-up (on input).
Page 114: Reading The Pin Value
Atmel AVR XMEGA D Figure 11-6. Output configuration - Wired-OR with optional pull-down. OUTn 11.3.4 Wired-AND In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are written to zero. When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal or an external pull-resistor.
Page 115: Input Sense Configuration
Atmel AVR XMEGA D Figure 11-8. Synchronization when reading a pin value. PERIPHERAL CLK INSTRUCTIONS lds r17, PORTx+IN SYNCHRONIZER FLIPFLOP 0x00 0xFF pd, max pd, min 11.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level.
Page 116: Port Interrupt
Atmel AVR XMEGA D 11.6 Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts must be enabled before they can be used. Which sense configurations can be used to generate interrupts is dependent on whether synchronous or asynchronous input sensing is used.
Page 117: Port Event
Atmel AVR XMEGA D Table 11-3. Limited asynchronous sense support. Sense Settings Supported Interrupt Description Rising edge Falling edge Both edges Pin value must be kept unchanged during wake up Low level Pin level must be kept unchanged during wake up 11.7...
Page 118: Slew Rate Control
Atmel AVR XMEGA D Figure 11-10. Port override signals and related logic. Pull Enable Pull Keep Pull Direction PINnCTRL Digital Input Disable (DID) DID Override Value DID Override Enable Wired AND/OR Slew Rate Limit Inverted I/O OUTn OUT Override Value...
Page 119: Multi-Pin Configuration
Atmel AVR XMEGA D 11.11 Multi-pin configuration The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written, while avoiding several pins being written the same way during identical write operations.
Page 120: Register Descriptions - Ports
Atmel AVR XMEGA D 11.13 Register Descriptions – Ports 11.13.1 DIR – Data Direction register +0x00 DIR[7:0] Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured as an output pin.
Page 121 Atmel AVR XMEGA D • Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
Page 122 Atmel AVR XMEGA D 11.13.8 OUTTGL – Data Output Value Toggle register +0x07 OUTTGL[7:0] OUTTGL Read/Write Initial Value • Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins.
Page 123 Atmel AVR XMEGA D • Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense config- uration for each pin is decided by the PINnCTRL registers.
Page 124 Atmel AVR XMEGA D • Bit 4 – USART0: USART0 Remap Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4]. • Bit 3 – TC0D: Timer/Counter 0 Output Compare D Setting this bit will move the location of OC0D from Px3 to Px7.
Page 125 Atmel AVR XMEGA D Table 11-4. Output/pull configuration. Description OPC[2:0] Group Configuration Output Configuration Pull Configuration TOTEM Totem-pole (N/A) BUSKEEPER Totem-pole Bus-keeper PULLDOWN Totem-pole Pull-down (on input) PULLUP Totem-pole Pull-up (on input) WIREDOR Wired-OR (N/A) WIREDAND Wired-AND (N/A) WIREDORPULL Wired-OR...
Page 126: Register Descriptions - Port Configuration
Atmel AVR XMEGA D 11.14 Register Descriptions – Port Configuration 11.14.1 MPCMASK – Multi-pin Configuration Mask register +0x00 MPCMASK[7:0] MPCMASK Read/Write Initial Value • Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n makes pin n part of the multi-pin configuration.
Page 127 Atmel AVR XMEGA D • Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the actual port registers.
Page 128 Atmel AVR XMEGA D Table 11-7 on page 128 shows the possible configurations. Table 11-7. Event output pin selection. EVOUT[1:0] Group Configuration Description Event output disabled Event channel 0 output on PORTC Event channel 0 output on PORTD Event channel 0 output on PORTE •...
Page 129 Atmel AVR XMEGA D • Bit 2:0 – EVOUTSEL[2:0]: Event Channel Output Selection These bits define which channel from the event system is output to the port pin. Table 11-10 on page 129 shows the available selections. Table 11-10. Event channel output selection.
Page 130: Register Descriptions - Virtual Port
Atmel AVR XMEGA D 11.15 Register Descriptions – Virtual Port 11.15.1 DIR – Data Direction +0x00 DIR[7:0] Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by VPCTRLA, vir- tual port-map control register A or VPCTRLB, virtual port-map control register B.
Page 131 Atmel AVR XMEGA D 11.15.4 INTFLAGS – Interrupt Flag register +0x03 – – – – – – INT1IF INT0IF INTFLAGS Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 132: Register Summary - Ports
Atmel AVR XMEGA D 11.16 Register Summary – Ports Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 DIR[7:0] +0x01 DIRSET DIRSET[7:0] +0x02 DIRCLR DIRCLR[7:0] +0x03 DIRTGL DIRTGL[7:0] +0x04...
Page 133: Interrupt Vector Summary - Ports
Atmel AVR XMEGA D 11.19 Interrupt Vector Summary - Ports Table 11-11. Port interrupt vectors and their word offset address. Offset Source Interrupt Description 0x00 INT0_vect Port interrupt vector 0 offset 0x02 INT1_vect Port interrupt vector 1 offset 8210C–AVR–09/11...
Page 134: Tc0/1 - 16-Bit Timer/Counter Type 0 And 1
12.2 Overview Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input cap- ture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
Page 135 Atmel AVR XMEGA D and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency gen- eration.
Page 136: Block Diagram
Atmel AVR XMEGA D 12.3 Block Diagram Figure 12-2 on page 136 shows a detailed block diagram of the timer/counter without the extensions. Figure 12-2. Timer/counter block diagram. Base Counter Clock Select PERBUF CTRLA Event Select CTRLD "count" OVF/UNF Counter "clear"...
Page 137: Clock And Event Sources
Atmel AVR XMEGA D 12.4 Clock and Event Sources The timer/counter can be clocked from the peripheral clock (clk ) or the event system, and Figure 12-3 shows the clock and event selection. Figure 12-3. Clock and event selection. Common...
Page 138: Counter Operation
Atmel AVR XMEGA D Figure 12-4. Period and compare double buffering. "data write" "write enable" CCxBUF UPDATE "match" When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case the buffer valid flag is set on the capture event, as shown in Figure 12-5.
Page 139 Atmel AVR XMEGA D Figure 12-6. Normal operation. CNT written "update" BOTTOM As shown in Figure 12-6, it is possible to change the counter value when the counter is running. The write access has higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed during normal operation.
Page 140: Capture Channel
Atmel AVR XMEGA D A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 12-8. This due to the fact that CNT and PER are continuously compared, and if a new TOP value that is lower than current CNT is written to PER, it will wrap before a compare match happen.
Page 141 Atmel AVR XMEGA D Figure 12-10. Event source selection for capture operation. Event System CH0MUX Event channel 0 CCA capture CH1MUX Event channel 1 CCB capture CH2MUX Event channel 2 CCC capture CH3MUX Event channel 3 CCD capture Rotate Event Source Selection The event action setting in the timer/counter will determine the type of capture that is done.
Page 142 Atmel AVR XMEGA D timer/counter restart until the event occurred. This can be used to calculate the frequency (f) of the signal: -- - Figure 12-12 on page 142 shows an example where the period of an external signal is measured twice.
Page 143: Compare Channel
Atmel AVR XMEGA D Figure 12-13. Pulse width capture of an external signal. Pulsewitdh (t external signal events "capture" BOTTOM 12.7.4 32-bit Input Capture Two timer/counters can be used together to enable true 32-bit input capture. In a typical 32-bit input capture setup, the overflow event of the least-significant timer is connected via the event system and used as the clock input for the most-significant timer.
Page 144 Atmel AVR XMEGA D 1. A waveform generation mode must be selected. 2. Event actions must be disabled. 3. The CC channels used must be enabled. This will override the corresponding port pin output register. 4. The direction for the associated port pin must be set to output.
Page 145 Atmel AVR XMEGA D Figure 12-15. Single-slope pulse width modulation. "update" Period (T) CCx=BOTTOM CCx=TOP "match" BOTTOM WG Output The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX).
Page 146 Atmel AVR XMEGA D Figure 12-16. Dual-slope pulse width modulation. "update" Period (T) CCx=BOTTOM CCx=TOP "match" BOTTOM WG Output Using dual-slope PWM results in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX).
Page 147: Interrupts And Events
Atmel AVR XMEGA D Figure 12-17. Port override for timer/counter 0 and 1. Waveform CCExEN INVEN 12.9 Interrupts and events The timer/counter can generate both interrupts and events. The counter can generate an inter- rupt on overflow/underflow, and each CC channel has a separate interrupt that is used for compare or capture.
Page 148: Register Description
Atmel AVR XMEGA D 12.11 Register Description 12.11.1 CTRLA – Control register A +0x00 – – – – CLKSEL[3:0] CTRLA Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 149 Atmel AVR XMEGA D • Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode...
Page 150 Atmel AVR XMEGA D 12.11.4 CTRLD – Control register D +0x03 EVACT[2:0] EVDLY EVSEL[3:0] CTRLD Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to...
Page 151 Atmel AVR XMEGA D Table 12-5. Timer event source selection. EVSEL[3:0] Group Configuration Event Source 0000 None 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1nnn Event channel n, n={0,...,3} 12.11.5 CTRLE – Control register E +0x04 –...
Page 152 Atmel AVR XMEGA D • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the timer error interrupt and select the interrupt level as described in ”Inter-...
Page 153 Atmel AVR XMEGA D • Bit 3:2 – CMD[1:0]: Command These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero. Table 12-7. Command selections Group Configuration...
Page 154 Atmel AVR XMEGA D 12.11.10 INTFLAGS – Interrupt Flag register +0x0C CCDIF CCCIF CCBIF CCAIF – – ERRIF OVFIF INTFLAGS Read/Write Initial Value • Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the corresponding CC channel.
Page 155 Atmel AVR XMEGA D +0x0F TEMP[7:0] TEMP Read/Write Initial Value 12.11.12 CNTL – Counter register L The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the timer/counter. CPU write access has priority over count, clear, or reload of the counter.
Page 156 Atmel AVR XMEGA D 12.11.15 PERH – Period register H +0x27 PER[15:8] PERH Read/Write Initial Value • Bit 7:0 – PER[15:8] These bits hold the MSB of the 16-bit period register. 12.11.16 CCxL – Compare or Capture x register L The CCxH and CCxL register pair represents the 16-bit value, CCx.
Page 157 Atmel AVR XMEGA D • Bit 7:0 – PERBUF[7:0] These bits hold the LSB of the 16-bit period buffer register. 12.11.19 PERBUFH – Timer/Counter Period Buffer H +0x37 PERBUF[15:8] PERBUFH Read/Write Initial Value • Bit 7:0 – PERBUF[15:8] These bits hold the MSB of the 16-bit period buffer register.
Page 158: Register Summary
Atmel AVR XMEGA D 12.12 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRLA – – – – CLKSEL[3:0] +0x01 CTRLB CCDEN CCCEN CCBEN CCAEN WGMODE[2:0]...
Page 159: Hi-Res - High-Resolution Extension
Atmel AVR XMEGA D 13. Hi-Res – High-Resolution Extension 13.1 Features • Increases waveform generator resolution up to 8x (3 bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 13.2...
Page 160: Register Description
Atmel AVR XMEGA D The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than four will have no visible output. 13.3 Register Description 13.3.1 CTRLA – Control register A +0x00 –...
Page 161: Awex - Advanced Waveform Extension
Atmel AVR XMEGA D 14. AWeX – Advanced Waveform Extension 14.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time –...
Page 162: Port Override
Atmel AVR XMEGA D output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override set- ting.
Page 163: Dead-Time Insertion
Atmel AVR XMEGA D Figure 14-2. Timer/counter extensions and port override logic. CWCM WG 0A OUT0 OC0A OCALS CCAEN INVEN0 OUTOVEN0 DTICCAEN Channel WG 0A OUTOVEN1 CCBEN INVEN1 OC0B OCAHS WG 0B OUT1 WG 0C OUT2 OC0C OCBLS CCCEN INVEN2...
Page 164: Pattern Generation
Atmel AVR XMEGA D The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. Figure 14-3 on page 164 shows the block diagram of one DTI generator. The four channels have a common register that controls the dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double buffered.
Page 165: Fault Protection
Atmel AVR XMEGA D cations. A block diagram of the pattern generator is shown in ”Pattern generator block diagram.” on page 165. For each port pin where the corresponding OOE bit is set, the multiplexer will out- put the waveform from CCA.
Page 166 Atmel AVR XMEGA D 14.6.2 Fault Restore Modes How the AWeX and timer/counter return from the fault state to normal operation after a fault, when the fault condition is no longer active, can be selected from one of two different modes: •...
Page 167: Register Description
Atmel AVR XMEGA D 14.7 Register Description 14.7.1 CTRL – Control register +0x00 – – CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN CTRL Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 168 Atmel AVR XMEGA D • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 4 – FDDBD: Fault Detection on Debug Break Detection By default, when this bit is cleared and fault protection is enabled, and OCD break request is treated as a fault.
Page 169 Atmel AVR XMEGA D • Bit 2 – FDF: Fault Detect Flag This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels enabled by FDEVMASK. This flag is cleared by writing a one to its bit location.
Page 170 Atmel AVR XMEGA D • Bit 7:0 – DTLS: Dead-time Low Side This register holds the number of peripheral clock cycles for the dead-time low side. 14.7.8 DTHS – Dead-time High Side register +0x09 DTHS[7:0] DTHS Read/Write Initial Value • Bit 7:0 – DTHS: Dead-time High Side This register holds the number of peripheral clock cycles for the dead-time high side.
Page 171: Register Summary
Atmel AVR XMEGA D • Bit 7:0 – OUTOVEN[7:0]: Output Override Enable These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position). The port direction is not overridden. 14.8 Register Summary Address Name...
Page 172: Rtc - Real-Time Counter
Atmel AVR XMEGA D 15. RTC — Real-Time Counter 15.1 Features • 16-bit resolution • Selectable clock source – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator • Programmable 10-bit clock prescaling •...
Page 173 Atmel AVR XMEGA D 15.2.1 Clock Domains The RTC is asynchronous, operating from a different clock source independently of the main system clock and its derivative clocks, such as the peripheral clock. For control and count regis- ter updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change has effect on the RTC.
Page 174: Register Descriptions
Atmel AVR XMEGA D 15.3 Register Descriptions 15.3.1 CTRL – Control register +0x00 – – – – – PRESCALER[2:0] CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 175 Atmel AVR XMEGA D 15.3.2 STATUS – Status register +0x01 – – – – – – – SYNCBUSY STATUS Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 176 Atmel AVR XMEGA D 15.3.4 INTFLAGS - Interrupt Flag register +0x03 – – – – – – COMPIF OVFIF INTFLAGS Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 177 Atmel AVR XMEGA D • Bit 7:0 - CNT[7:0]: Counter Value Low These bits hold the LSB of the 16-bit real-time counter value. 15.3.7 CNTH – Counter Register High +0x09 CNT[15:8] CNTH Read/Write Initial Value • Bit 7:0 – CNT[15:8]: Counter Value High These bits hold the MSB of the 16-bit real-time counter value.
Page 178 Atmel AVR XMEGA D 15.3.10 COMPL – Compare Register Low The COMPH and COMPL register pair represent the 16-bit value, COMP. COMP is constantly compared with the counter value (CNT). A compare match will set COMPIF in the INTFLAGS register. Reading and writing 16-bit values requires special attention. Refer ”Accessing 16-bit...
Page 179: Register Summary
Atmel AVR XMEGA D 15.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – PRESCALER[2:0] +0x01 STATUS – – – –...
Page 180: Twi - Two-Wire Interface
Atmel AVR XMEGA D 16. TWI – Two-Wire Interface 16.1 Features • Bidirectional, two-wire communication interface – Phillips I C compatible – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – Single bus master operation –...
Page 181: General Twi Bus Concepts
Atmel AVR XMEGA D 16.3 General TWI Bus Concepts The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up resistors provide a high level on the lines when none of the connected devices are driving the The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
Page 182 Atmel AVR XMEGA D Figure 16-2. Basic TWI transaction diagram topology for a 7-bit address bus . 6 ... 0 7 ... 0 7 ... 0 ADDRESS DATA DATA ACK/NACK ADDRESS DATA DATA Direction Address Packet Data Packet #0 Data Packet #1...
Page 183 Atmel AVR XMEGA D 16.3.3 Bit Transfer As illustrated by Figure 16-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line. Consequently the SDA value can only be changed during the low period of the clock.
Page 184 Atmel AVR XMEGA D Figure 16-5. Master write transaction. Transaction Address Packet Data Packet ADDRESS DATA DATA N data packets Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP condition (P) directly after the address packet.
Page 185 Atmel AVR XMEGA D Three types of clock stretching can be defined, as shown in Figure 16-8. Figure 16-8. Clock stretching bit 7 bit 6 bit 0 ACK/NACK Wakeup clock Periodic clock Random clock stretching stretching stretching Note: 1. Clock stretching is not supported by all I C slaves and masters.
Page 186: Twi Bus State Logic
Atmel AVR XMEGA D Figure 16-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Page 187: Twi Master Operation
Atmel AVR XMEGA D Figure 16-11. Bus state, state diagram. RESET UNKNOWN (0b00) P + Timeout IDLE BUSY P + Timeout (0b01) (0b11) Command P Arbitration Write ADDRESS Lost OWNER (0b10) Write ADDRESS(Sr) After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter idle by writing to the bus state bits accordingly.
Page 188 Atmel AVR XMEGA D When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and will in most cases require software interaction. Figure 16-12 shows the TWI master operation.
Page 189: Twi Slave Operation
Atmel AVR XMEGA D 16.5.1.2 Case M2: Address packet transmit complete - Address not acknowledged by slave If no slave device responds to the address, the master write interrupt flag and the master received acknowledge flag are set. The clock hold is active at this point, preventing further activ- ity on the bus.
Page 190 Atmel AVR XMEGA D Figure 16-13. TWI slave operation. SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT ADDRESS DATA Driver software DATA The master provides data on the bus Interrupt on STOP Condition Enabled Slave provides data on the bus Collision Release...
Page 191: Enabling External Driver Interface
Atmel AVR XMEGA D received. Data, repeated START, or STOP can be received after this. If NACK is sent, the slave will wait for a new START condition and address match. 16.6.1.3 Case S3: Collision If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge output from the slave logic.
Page 192: Register Description - Twi
Atmel AVR XMEGA D 16.8 Register Description – 16.8.1 CTRL – Common Control Register +0x00 – – – – – SDAHOLD[1:0] EDIEN CTRL Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 193: Register Description - Twi Master
Atmel AVR XMEGA D 16.9 Register Description – TWI Master – 16.9.1 CTRLA Control register A +0x00 INTLVL[1:0] RIEN WIEN ENABLE – – – CTRLA Read/Write Initial Value – • Bit 7:6 INTLVL[1:0]: Interrupt Level These bits select the interrupt level for the TWI master interrupt, as described in ”Interrupts and...
Page 194 Atmel AVR XMEGA D Table 16-3. TWI master inactive bus timeout settings. TIMEOUT[1:0] Group Configuration Description DISABLED Disabled, normally used for I 50US 50µs, normally used for SMBus at 100kHz 100US 100µs 200US 200µs – • Bit 1 QCEN: Quick Command Enable When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address (read or write interrupt).
Page 195 Atmel AVR XMEGA D STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Table 16-5. CMD bits description. Group CMD[1:0]...
Page 196 Atmel AVR XMEGA D – • Bit 5 CLKHOLD: Clock Hold This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.
Page 197 Atmel AVR XMEGA D The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency. The frequency relation can be expressed by using the following equation: --------------------------------------- - [Hz] TWMBR) The BAUD register must be set to a value that results in a TWI bus clock frequency (f...
Page 198: Register Description - Twi Slave
Atmel AVR XMEGA D register can only be accessed when the SCL line is held low by the master; i.e., when CLKHOLD is set. In master write mode, writing the DATA register will trigger a data byte transfer followed by the master receiving the acknowledge bit from the slave.
Page 199 Atmel AVR XMEGA D – • Bit 0 SMEN: Smart Mode Enable This bit enables smart mode. When Smart mode is enabled, the acknowledge action, as set by the ACKACT bit in the CTRLB register, is sent immediately after reading the DATA register.
Page 200 Atmel AVR XMEGA D Table 16-8. TWI slave command. (Continued) Group CMD[1:0] Configuration Operation Used in response to an address byte (APIF is set) Execute acknowledge action succeeded by reception of next byte Execute acknowledge action succeeded by DIF being set...
Page 201 Atmel AVR XMEGA D – • Bit 4 RXACK: Received Acknowledge This flag contains the most recently received acknowledge bit from the master. This is a read- only flag. When read as zero, the most recent acknowledge bit from the maser was ACK, and when read as one, the most recent acknowledge bit was NACK.
Page 202 Atmel AVR XMEGA D When using 10-bit addressing, the address match logic only supports hardware address recog- nition of the first byte of a 10-bit address. By setting ADDR[7:1] = 0b11110nn, ”nn” represents bits 9 and 8 of the slave address. The next byte received is bits 7 to 0 in the 10-bit address, and this must be handled by software.
Page 203 Atmel AVR XMEGA D – • Bit 0 ADDREN: Address Enable By default, this bit is zero, and the ADDRMASK bits acts as an address mask to the ADDR reg- ister. If this bit is set to one, the slave address match logic responds to the two unique addresses in ADDR and ADDRMASK.
Page 204: Register Summary - Twi
Atmel AVR XMEGA D 16.11 Register Summary - TWI Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – – – SDAHOLD EDIEN +0x01 MASTER...
Page 205: Spi - Serial Peripheral Interface
Atmel AVR XMEGA D 17. SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, three-wire synchronous data transfer • Master or slave operation • Lsb first or msb first data transfer • Eight programmable bit rates • Interrupt flag at the end of transmission •...
Page 206: Master Mode
Atmel AVR XMEGA D When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 17-1. The pins with user-defined direction must be configured from software to have the correct direction according to the application.
Page 207: Data Modes
Atmel AVR XMEGA D 17.5 Data Modes There are four combinations of SCK phase and polarity with respect to serial data. The SPI data transfer formats are shown in Figure 17-2. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
Page 208: Register Description
Atmel AVR XMEGA D 17.6 Register Description 17.6.1 CTRL – Control register +0x00 CLK2X ENABLE DORD MASTER MODE[1:0] PRESCALER[1:0] CTRL Read/Write Initial Value • Bit 7 – CLK2X: Clock Double When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see...
Page 209 Atmel AVR XMEGA D Table 17-3. Relationship between SCK and the peripheral clock (Clk ) frequency. CLK2X PRESCALER[1:0] SCK Frequency /128 17.6.2 INTCTRL – Interrupt Control register +0x01 – – – – – – INTLVL[1:0] INTCTRL Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use.
Page 210 Atmel AVR XMEGA D • Bit 6 – WRCOL: Write Collision Flag The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared by first reading the STATUS register when WRCOL is set, and then accessing the DATA register.
Page 211: Register Summary
Atmel AVR XMEGA D 17.7 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL CLK2X ENABLE DORD MASTER MODE[1:0] PRESCALER[1:0] +0x01 INTCTRL – – – –...
Page 212: Usart
Atmel AVR XMEGA D 18. USART 18.1 Features • Full-duplex operation • Asynchronous or synchronous operation – Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency •...
Page 213 Atmel AVR XMEGA D Figure 18-1. USART block diagram. Clock Generator BSEL [H:L] BAUD RATE GENERATOR FRACTIONAL DIVIDE SYNC LOGIC CONTROL Transmitter DATA (Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RECOVERY...
Page 214: Clock Generation
Atmel AVR XMEGA D 18.3 Clock Generation The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported: normal and double-speed asynchronous mode, master and slave synchronous mode, and master SPI mode.
Page 215 Atmel AVR XMEGA D Table 18-1. Equations for calculating baud rate register settings. Operating Mode Conditions Baud Rate Calculation BSEL Value Calculation BSCALE ≥ 0 ------------------------------------------------ 1 – BSEL ------------------------------------------------------------- - ≤ BAUD ---------- - BSCALE BSCALE ⋅ ⋅ Asynchronous normal...
Page 216 Atmel AVR XMEGA D 18.3.3 Double Speed Operation Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock frequencies. When this is enabled, the baud rate for a given asynchronous baud rate setting shown in Table 18-1 on page 215 will be doubled.
Page 217: Frame Formats
Atmel AVR XMEGA D Table 18-2. INVEN and UCPHA functionality. SPI Mode INVEN UCPHA Leading Edge Trailing Edge Rising, sample Falling, setup Rising, setup Falling, sample Falling, sample Rising, setup Falling, setup Rising, sample The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Page 218: Usart Initialization
Atmel AVR XMEGA D Figure 18-5. Frame formats. FRAME (IDLE) Sp1 [Sp2] (St / IDLE) Start bit, always low. Data bits (0 to 8). Parity bit, may be odd or even. Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). The IDLE state is always high.
Page 219: Data Reception - The Usart Receiver
Atmel AVR XMEGA D 18.6.1 Sending Frames A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent. The data in the transmit buffer are moved to the shift register when the shift register is empty and ready to send a new frame.
Page 220: Asynchronous Data Reception
Atmel AVR XMEGA D 18.7.3 Parity Checker When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set.
Page 221 Atmel AVR XMEGA D 18.8.2 Asynchronous Data Recovery The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit. Figure 18-7 on page 221 shows the sampling process of data and parity bits.
Page 222 Atmel AVR XMEGA D ------------------------------------------ - ----------------------------------- D S ⋅ slow fast – Sum of character size and parity size (D = 5 to 10 bits). Samples per bit. S = 16 for normal speed mode and S = 8 for double speed mode.
Page 223: Fractional Baud Rate Generation
Atmel AVR XMEGA D 18.9 Fractional Baud Rate Generation Fractional baud rate generation is possible for asynchronous operation due to the relatively high number of clock cycles for each frame. Each bit is sampled sixteen times, but only the three mid- dle samples are of importance.
Page 224: Usart In Master Spi Mode
Atmel AVR XMEGA D Figure 18-9. Fractional baud rate example. Baud counter Ideal baud clock Baud counter Fractional baud clock 18.10 USART in Master SPI Mode Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to serve as the serial input.
Page 225: Multiprocessor Communication Mode
Atmel AVR XMEGA D • Interrupt timing is not compatible • Pin control differs due to the master-only operation of the USART in SPI master mode A comparison of the USART in master SPI mode and the SPI pins is shown Table 18-5.
Page 226 Atmel AVR XMEGA D For devices with more than one USART, IRCOM mode can be enabled for only one USART at a time. For details, refer to ”IRCOM - IR Communication Module” on page 234 8210C–AVR–09/11...
Page 227: Register Description
Atmel AVR XMEGA D 18.14 Register Description 18.14.1 DATA – Data register RXB[[7:0] +0x00 TXB[[7:0] Read/Write Initial Value The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB) share the same I/O address and is referred to as USART data register (DATA). The TXB register is the destination for data written to the DATA register location.
Page 228 Atmel AVR XMEGA D • Bit 5 – DREIF: Data Register Empty Flag This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is one when the transmit buffer is empty and zero when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register.
Page 229 Atmel AVR XMEGA D 18.14.3 CTRLA – Control register A +0x03 – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] CTRLA Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 230 Atmel AVR XMEGA D shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. • Bit 2 – CLK2X: Double Transmission Speed Setting this bit will reduce the divisor of the baud rate divider from16 to 8, effectively doubling the transfer rate for asynchronous communication modes.
Page 231 Atmel AVR XMEGA D • Bits 5:4 – PMODE[1:0]: Parity Mode These bits enable and set the type of parity generation according to Table 18-7 on page 231. When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame.
Page 232 Atmel AVR XMEGA D • Bit 2 – UDORD: Data Order This bit is only for master SPI mode, and this bit sets the frame format. When written to one, the lsb of the data word is transmitted first. When written to zero, the msb of the data word is trans- mitted first.
Page 233: Register Summary
Atmel AVR XMEGA D 18.15 Register Summary 18.15.1 Register Description - USART Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 DATA DATA[7:0] +0x01 STATUS RXCIF TXCIF DREIF FERR...
Page 234: Ircom - Ir Communication Module
Atmel AVR XMEGA D 19. IRCOM - IR Communication Module 19.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable –...
Page 235 Atmel AVR XMEGA D For transmission, three pulse modulation schemes are available: • 3/16 of the baud rate period • Fixed programmable pulse time based on the peripheral clock frequency • Pulse modulation disabled For reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical 0 is used.
Page 236: Registers Description
Atmel AVR XMEGA D 19.3 Registers Description 19.3.1 TXPLCTRL – Transmitter Pulse Length Control Register +0x01 TXPLCTRL[7:0] TXPLCTRL Read/Write Initial Value • Bit 7:0 – TXPLCTRL[7:0]: Transmitter Pulse Length Control This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have no effect if IRCOM mode is not selected by a USART.
Page 237: Register Summary
Atmel AVR XMEGA D • Bit 3:0 – EVSEL [3:0]: Event Channel Selection These bits select the event channel source for the IRCOM receiver according to Table 19-1 on page 237. If event input is selected for the IRCOM receiver, the input from the USART’s RX pin is automatically disabled.
Page 238: Crc - Cyclic Redundancy Check
Atmel AVR XMEGA D 20. CRC – Cyclic Redundancy Check 20.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space •...
Page 239: Operation
Atmel AVR XMEGA D 20.3 Operation The data source for the CRC module must be selected in software as either flash memory or the I/O interface. The CRC module then takes data input from the selected source and generates a checksum based on these data.
Page 240: Crc Using The I/O Interface
Atmel AVR XMEGA D 20.5 CRC using the I/O Interface CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the DATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte.
Page 241: Register Description
Atmel AVR XMEGA D 20.6 Register Description 20.6.1 CTRL – Control register +0x00 RESET[1:0] CRC32 – SOURCE[3:0] CTRL Read/Write Initial Value • Bit 7:6 – RESET[1:0]: Reset These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be reset one peripheral clock cycle after the RESET[1] bit is set.
Page 242 Atmel AVR XMEGA D Table 20-2. CRC source select (Continued). SOURCE[3:0] Group configuration Description 0110 — Reserved for future use 0111 — Reserved for future use 1xxx — Reserved for future use 20.6.2 STATUS – Status register +0x02 – –...
Page 243 Atmel AVR XMEGA D possible to write RESET to reset all bits to one. It is possible to write these registers only when the CRC module is disabled. If NVM is selected as the source, reading CHECKSUM will return a zero value until the BUSY flag is cleared.
Page 244: Register Sumary
Atmel AVR XMEGA D 20.7 Register Sumary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL RESET[1:0] CRC32 – SOURCE[3:0] +0x01 STATUS – – – – – –...
Page 245: Adc - Analog-To-Digital Converter
Atmel AVR XMEGA D 21. ADC – Analog-to-Digital Converter 21.1 Features • 12-bit resolution • Up to 300 thousand samples per second – Down to 2.3µs conversion time with 8-bit resolution – Down to 3.35µs conversion time with 12-bit resolution •...
Page 246: Input Sources
Atmel AVR XMEGA D Figure 21-1. ADC overview. S&H Σ 2 bits Compare ADC0 Register • • • < Stage Stage ADC15 > Threshold (Int Req) Internal CH0 Result signals Digital Correction Logic ADC0 • • • ADC7 Internal 1.00V...
Page 247 Atmel AVR XMEGA D Figure 21-2. Differential measurement without gain. ADC0 • • • ADC15 ADC0 • • • ADC3 INTGND 21.3.2 Differential Input with Gain When differential input with gain is enabled, all input pins can be selected as positive input, and input pins 4 to 7 can be selected as negative input.
Page 248 Atmel AVR XMEGA D Figure 21-4. Single-ended measurement in signed mode. ADC0 • • • ADC15 In unsigned mode, the negative input is connected to half of the voltage reference (VREF) volt- age minus a fixed offset. The nominal value for the offset is: ΔV...
Page 249: Sampling Time Control
Atmel AVR XMEGA D is lower than that of the ADC. Refer to the ADC characteristics in the device datasheets for details. For differential measurement Pad Ground (Gnd) and Internal Gnd can be selected as negative input. Pad Gnd is the gnd level on the pin and identical or very close to the external gnd. Internal Gnd is the internal device gnd level.
Page 250: Conversion Result
Atmel AVR XMEGA D Figure 21-8. ADC voltage reference selection Internal 1.00V Internal VCC/1.6V VREF Internal VCC/2.0V AREFA AREFB 21.6 Conversion Result The result of the analog-to-digital conversion is written to the corresponding channel result regis- ters. The ADC is either in signed or unsigned mode. This setting is global for the ADC and all ADC channels.
Page 251: Compare Function
Atmel AVR XMEGA D Figure 21-9. Signed differential input (with gain), input range, and result representation. VREF Binary 16-bit result register GAIN 2047 0111 1111 1111 0000 0111 1111 1111 2046 0111 1111 1110 0000 0111 1111 1110 VINN 2045...
Page 252: Starting A Conversion
Atmel AVR XMEGA D 21.8 Starting a Conversion Before a conversion is started, the input source must be selected. An ADC conversion can be started either by the application software writing to the start conversion bit or from any events in the event system.
Page 253 Atmel AVR XMEGA D 21.9.1 Single Conversion without Gain Figure 21-13 on page 253 shows the ADC timing for a single conversion without gain. The writ- ing of the start conversion bit, or the event triggering the conversion (START), must occur at least one peripheral clock cycle before the ADC clock cycle on which the conversion starts (indi- cated with the grey slope of the START trigger).
Page 254 Atmel AVR XMEGA D Figure 21-15. ADC timing for one single conversion with 2x gain. START ADC SAMPLE AMPLIFY CONVERTING BIT GAINSTAGE SAMPLE AMPLIFY ADC SAMPLE CONVERTING BIT Figure 21-16. ADC timing for one single conversion with 8x gain. START...
Page 255: Adc Input Model
Atmel AVR XMEGA D Figure 21-17. ADC timing for one single conversion with 64x gain. START ADC SAMPLE AMPLIFY CONVERTING BIT GAINSTAGE SAMPLE AMPLIFY ADC SAMPLE CONVERTING BIT 21.10 ADC Input Model The voltage input must charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy.
Page 256: Interrupts And Events
Atmel AVR XMEGA D In order to achieve n bits of accuracy, the source output resistance, R , must be less than source the ADC input resistance on a pin: ≤ ---------------------------------------------- - R – – source channel switch ⋅...
Page 257: Register Description - Adc
Atmel AVR XMEGA D 21.14 Register Description – 21.14.1 CTRLA – Control register A +0x00 – – – – – CH0START FLUSH ENABLE CTRLA Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 258 Atmel AVR XMEGA D Table 21-1. ADC current limitations. CURRLIMIT[1:0] Group Configuration Description No limit Low current limit, max. sampling rate 1.5MSPS Medium current limit, max. sampling rate 1MSPS HIGH High current limit, max. sampling rate 0.5MSPS • Bit 4 – CONVMODE: Conversion Mode This bit controls whether the ADC will work in signed or unsigned mode.
Page 259 Atmel AVR XMEGA D • Bits 6:4 – REFSEL[2:0]: Reference Selection These bits selects the reference for the ADC according to Table 21-3 on page 259. Table 21-3. ADC reference selection. REFSEL[2:0] Group Configuration Description INT1V 10/11 of bandgap (1.0V) INTVCC /1.6...
Page 260 Atmel AVR XMEGA D Table 21-4. ADC event channel select. EVSEL[1:0] Group Configuration Selected Event Lines Event channel 0 selected inputs Event channel 1 selected inputs Event channel 2 selected inputs Event channel 3 selected inputs • Bit 2:0 – EVACT[2:0]: Event Mode These bits select and limit how many of the selected event input channel are used, and also fur- ther limit the ADC channels triggers.
Page 261 Atmel AVR XMEGA D Table 21-6. ADC prescaler settings (Continued). DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 21.14.6 INTFLAGS – Interrupt Flag register +0x06 – – – – – – – CH0IF INTFLAGS Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use.
Page 262 Atmel AVR XMEGA D • Bit 7:0 – CAL[7:0]: ADC Calibration value These are the eight lsbs of the 12-bit CAL value. 21.14.9 CALH – Calibration Value register +0x0D – – – – CAL[11:8] CALH Read/Write Initial Value • Bit 3:0 – CAL[11:8]: Calibration value These are the four msbs of the 12-bit CAL value.
Page 263 Atmel AVR XMEGA D 21.14.11 CH0RESL – Channel 0 Result register Low 12-/8-bit, right CHRES[7:0] 12-bit, left CHRES[3:0] – – – – Read/Write Initial Value 21.14.11.1 12-/8-bit Mode • Bit 7:0 – CHRES[7:0]: Channel Result Low These are the eight lsbs of the ADC result.
Page 264: Register Description - Adc Channel
Atmel AVR XMEGA D 21.15 Register Description - ADC Channel 21.15.1 CTRL – Control Register +0x00 START – – GAIN[2:0] INPUTMODE[1:0] CTRL Read/Write Initial Value • Bit 7 – START: START Conversion on Channel Setting this bit will start a conversion on the channel. The bit is cleared by hardware when the conversion has started.
Page 265 Atmel AVR XMEGA D Table 21-9. Channel input modes, CONVMODE=1 (signed mode). INPUTMODE[1:0] Group Configuration Description INTERNAL Internal positive input signal SINGLEENDED Single-ended positive input signal DIFF Differential input signal DIFFWGAIN Differential input signal with gain 21.15.2 MUXCTRL – MUX Control registers The MUXCTRL register defines the input source for the channel.
Page 266 Atmel AVR XMEGA D Table 21-11. ADC MUXPOS configuration when INPUTMODE[1:0] = 01 (single-ended), INPUTMODE[1:0] = 10 (differential) or INPUTPMODE[1:0] = 1 (differential with gain) is used. 0111 PIN7 ADC7 pin 1000 PIN8 ADC8 pin 1001 PIN9 ADC9 pin 1010...
Page 267 Atmel AVR XMEGA D Table 21-13. ADC MUXNEG configuration, INPUTMODE[1:0] = 11, differential with gain Reserved Reserved PAD ground 21.15.3 INTCTRL – Interrupt Control registers +0x02 – – – – INTMODE[1:0} INTLVL[1:0] INTCTRL Read/Write Initial Value • Bits 7:4 – Reserved These bits are unused and reserved for future use.
Page 268 Atmel AVR XMEGA D when the ADC channel interrupt vector is executed. The bit can also be cleared by writing a one to the bit location. 21.15.5 RESH – Result register High For all result registers and with any ADC result resolution, a signed number is represented in 2’s complement form, and the msb represents the sign bit.
Page 269 Atmel AVR XMEGA D 21.15.6.2 12-bit Mode, Left Adjusted • Bit 7:4 – RES[3:0]: Result Low These are the four lsbs of the 12-bit ADC result. • Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 270: Register Summary - Adc
Atmel AVR XMEGA D 21.16 Register Summary - ADC This is the register summary when the ADC is configured to give standard 12-bit results. The register summaries for 8-bit and 12-bit left adjusted will be similar, but with some changes in the result registers, CH0RESH and CH0RESL.
Page 271: Ac - Analog Comparator
Atmel AVR XMEGA D 22. AC – Analog Comparator 22.1 Features • Selectable propagation delay versus current consumption • Selectable hysteresis – Small – Large • Analog comparator output available on pin • Flexible input selection – All pins on the port –...
Page 272: Input Sources
Atmel AVR XMEGA D Figure 22-1. Analog comparator overview. Pin Input AC0OUT Pin Input Hysteresis Enable Voltage Interrupt Interrupts Scaler Interrupt Sensititivity Mode Control ACnMUXCTRL ACnCTRL WINCTRL & Window Events Function Bandgap Enable Hysteresis Pin Input AC1OUT Pin Input 22.3 Input Sources Each analog comparator has one positive and one negative input.
Page 273: Window Mode
Atmel AVR XMEGA D (falling edge). Events are generated at all times for the same condition as the interrupt, regard- less of whether the interrupt is enabled or not. 22.6 Window Mode Two analog comparators on the same port can be configured to work together in window mode.
Page 274: Register Description
Atmel AVR XMEGA D 22.8 Register Description 22.8.1 ACnCTRL – Analog Comparator n Control register +0x00 / +0x01 INTMODE[1:0] INTLVL[1:0] – HYSMODE[2:0] ENABLE ACnCTRL Read/Write Initial Value • Bit 7:6 – INTMODE[1:0]: Interrupt Modes These bits configure the interrupt mode for analog comparator n according to Table 22-1.
Page 275 Atmel AVR XMEGA D 22.8.2 ACnMUXCTRL – Analog Comparator n Mux Control register – +0x02 / +0x03 – MUXPOS[2:0] MUXNEG[2:0] ACnMUXCTRL Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 276 Atmel AVR XMEGA D 22.8.3 CTRLA – Control register A +0x04 – – – – – – AC1OUT AC0OUT CTRLA Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Page 277 Atmel AVR XMEGA D • Bits 3:2 – WINTMODE[1:0]: Window Interrupt Mode Settings These bits configure the interrupt mode for the analog comparator window mode according to Table 22-5. Table 22-5. Window mode interrupt settings. WINTMODE[1:0] Group Configuration Description ABOVE...
Page 278 Atmel AVR XMEGA D This flag is automatically cleared when the analog comparator window interrupt vector is exe- cuted. The flag can also be cleared by writing a one to its bit location. • Bit 1 – AC1IF: Analog Comparator 1 Interrupt Flag This is the interrupt flag for AC1.
Page 279 Atmel AVR XMEGA D • Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:0 – CALIB[3:0]: Current Source Calibration The constant current source is calibrated during production.
Page 280: Register Summary
Atmel AVR XMEGA D 22.9 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 AC0CTRL INTMODE[1:0] INTLVL[1:0] – HYSMODE[1:0] ENABLE +0x01 AC1CTRL INTMODE[1:0] INTLVL[1:0] – HYSMODE[1:0] ENABLE...
Page 281: Program And Debug Interface
It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level.
Page 282: Pdi Physical
PDI_DATA Connector The remainder of this section is intended for use only by third parties developing programmers or programming support for Atmel AVR XMEGA devices. 23.3.1 Enabling The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width data).
Page 283 Atmel AVR XMEGA D Next, continue to keep the PDI_DATA line high for 16 PDI_CLK cycles. The first PDI_CLK cycle must start no later than 100µs after the RESET functionality of the Reset pin is disabled. If this does not occur in time, the enabling procedure must start over again. The enable sequence is...
Page 284 Atmel AVR XMEGA D Figure 23-5. Characters and timing for the PDI physical layer. 1 DATA character START STOP 1 BREAK character BREAK 1 IDLE character IDLE 23.3.4 Serial Transmission and Reception The PDI physical layer is either in transmit (TX) or receive (RX) mode. By default, it is in RX mode, waiting for a start bit.
Page 285 Atmel AVR XMEGA D When the PDI is in TX mode, a BREAK character signaled by the programmer will not be inter- preted as a BREAK, but will instead cause a generic data collision. When the PDI is in RX mode, a BREAK character will be recognized as a BREAK.
Page 286: Pdi Controller
Atmel AVR XMEGA D Figure 23-8. Driving data out on the PDI_DATA using a bus keeper. PDI_CLK Output enable PDI Output PDI_DATA If the programmer and the PDI both drive the PDI_DATA line at the same time, drive contention will occur, as illustrated in Figure 23-9 on page 286.
Page 287 Atmel AVR XMEGA D or it may involve data being returned to the programmer (e.g., a data byte is read from a location within the device). 23.4.1 Accessing Internal Interfaces After an external programmer has established communication with the PDI, the internal inter- faces are not accessible, by default.
Page 288 Atmel AVR XMEGA D 23.4.5.1 LDS - Load Data from PDIBUS Data Space using Direct Addressing The LDS instruction is used to load data from the PDIBUS data space for read out. The LDS instruction is based on direct addressing, which means that the address must be given as an argument to the instruction.
Page 289 Atmel AVR XMEGA D 23.4.5.6 STCS - Store Data to PDI Control and Status Register Space The STCS instruction is used to store data that are serially shifted into the physical layer shift register to locations within the PDI control and status registers. The STCS instruction supports only direct addressing and single-byte access.
Page 290: Register Description - Pdi Instruction And Addressing Registers
Atmel AVR XMEGA D Figure 23-10. PDI instruction set summary. Size A Size B LDCS (LDS Control/Status) REPEAT STCS (STS Control/Status) Size A/B Size A - Address size (direct access) Byte Word (2 Bytes) 3 Bytes Long (4 Bytes) CS Address...
Page 291 Atmel AVR XMEGA D addressing is based on an address already stored in the pointer register prior to the access itself. Indirect data access can be optionally combined with pointer register post-increment. The indirect access mode has an option that makes it possible to load or read the pointer register without accessing any other registers.
Page 292: Register Description - Pdi Control And Status Registers
Atmel AVR XMEGA D 23.6 Register Description – PDI Control and Status Registers The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI itself.
Page 293: Register Summary
Atmel AVR XMEGA D – • Bit 2:0 GUARDTIME[2:0]: Guard Time These bits specify the number of IDLE bits of guard time that are inserted in between PDI recep- tion and transmission direction changes. The default guard time is 128 IDLE bits, and the...
Page 294: Memory Programming
24.2 Overview This section describes how to program the nonvolatile memory (NVM) in Atmel AVR XMEGA devices, and covers both self-programming and external programming. The NVM consists of the flash program memory, user signature and calibration rows, fuses and lock bits, and EEPROM data memory.
Page 295: Nvm Controller
Atmel AVR XMEGA D The device can be locked to prevent reading and/or writing of the NVM. There are separate lock bits for external programming access and self-programming access to the boot loader section, application section, and application table section.
Page 296: Flash And Eeprom Page Buffers
Atmel AVR XMEGA D This ensures that the given command is executed and the operations finished before the start of a new operation. The external programmer or application software must ensure that the NVM is not addressed when it is busy with a programming operation.
Page 297: Flash And Eeprom Programming Sequences
Atmel AVR XMEGA D selected page buffer location to tag them. When performing an EEPROM page erase, the actual value of the tagged location does not matter. The EEPROM page buffer is automatically erased after: • A system reset • Executing the write EEPROM page command •...
Page 298: Protection Of Nvm
Atmel AVR XMEGA D Alternative 1: • Fill the EEPROM page buffer with the selected number of bytes • Perform a EEPROM page erase • Perform a EEPROM page write Alternative 2: • Fill the EEPROM page buffer with the selected number of bytes •...
Page 299 Atmel AVR XMEGA D out the program memory code. It has the capability to write into the entire flash, including the boot loader section. The boot loader can thus modify itself, and it can also erase itself from the flash if the feature is not needed anymore.
Page 300 Atmel AVR XMEGA D Figure 24-1. Flash addressing for self-programming. Z-Pointer FPAGE FWORD Low/High Byte select for (E)LPM PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE FPAGE PROGRAM MEMORY PAGE FWORD PAGE INSTRUCTION WORD PAGEEND FLASHEND 24.11.2 NVM Flash Commands...
Page 301 Atmel AVR XMEGA D Table 24-2. Flash self-programming commands (Continued). Data Change Address Registe CMD[6:0] Group Configuration Description Trigger Halted Busy Protected Pointer 0x02E WRITE_FLASH_PAGE Write flash page Z-pointer 0x2F ERASE_WRITE_FLASH_PAGE Erase and write flash page Z-pointer 0x3A FLASH_RANGE_CRC Flash range CRC...
Page 302 Atmel AVR XMEGA D 24.11.2.3 Load Flash Page Buffer The load flash page buffer command is used to load one word of data into the flash page buffer. 1. Load the NVM CMD register with the load flash page buffer command.
Page 303 Atmel AVR XMEGA D In order to use the flash range CRC command, all the boot lock bits must be unprogrammed (no locks). The command execution will be aborted if the boot lock bits for an accessed location are set.
Page 304 Atmel AVR XMEGA D 1. Load the Z-pointer with the flash page to write. The page address must be written to FPAGE. Other bits in the Z-pointer will be ignored during this operation. 2. Load the NVM CMD register with the erase and write application section/boot loader section page command.
Page 305 Atmel AVR XMEGA D 1. Load the Z-pointer with the byte address to read. 2. Load the NVM CMD register with the read user signature row / calibration row command 3. Execute the LPM instruction. The destination register will be loaded during the execution of the LPM instruction.
Page 306 Atmel AVR XMEGA D Load the NVM CMD register with the read fuses command. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The result will be available in the NVM DATA0 register. The CPU is halted during the complete execution of the command.
Page 307 Atmel AVR XMEGA D When EEPROM memory mapping is enabled, loading a data byte into the EEPROM page buffer can be performed through direct or indirect store instructions. Only the least-significant bits of the EEPROM address are used to determine locations within the page buffer, but the complete memory mapped EEPROM address is always required to ensure correct address mapping.
Page 308 Atmel AVR XMEGA D 24.11.5.2 Erase EEPROM Page Buffer The erase EEPROM page buffer command is used to erase the EEPROM page buffer. 1. Load the NVM CMD register with the erase EEPROM buffer command. 2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming.
Page 309: External Programming
Atmel AVR XMEGA D The BUSY flag in the NVM STATUS register will be set until the operation is finished. 24.11.5.7 Read EEPROM The read EEPROM command is used to read one byte from the EEPROM. Load the NVM CMD register with the read EEPROM command.
Page 310 Atmel AVR XMEGA D Figure 24-3. Memory map for PDI accessing the data and program memories. TOP=0x1FFFFFF FLASH_BASE = 0x0800000 EPPROM_BASE = 0x08C0000 FUSE_BASE = 0x08F0020 DATAMEM_BASE = 0x1000000 DATAMEM 16 MB (mapped IO/SRAM) APP_BASE = FLASH_BASE BOOT_BASE = FLASH_BASE + SIZE_APPL...
Page 311 Atmel AVR XMEGA D data registers, but the NVM controller must be loaded with the correct command (i.e., to read from any NVM, the controller must be loaded with the NVM read command before loading data from the PDIBUS address space). For the reminder of this section, all references to reading and...
Page 312 Atmel AVR XMEGA D Change CMD[6:0] Commands / Operation Trigger Protected NVM Busy 0x38 Application section CRC CMDEX Boot Loader Section 0x68 Erase boot section PDI write 0x2A Erase boot loader section page PDI write 0x2C Write boot loader section page...
Page 313 Atmel AVR XMEGA D 1. Load the NVM CMD register with the read NVM command. 2. Read the selected memory address by executing a PDI read operation. Dedicated read EEPROM, read fuse, read signature row, and read calibration row commands are also available for the various memory sections.
Page 314 Atmel AVR XMEGA D 24.12.3.7 Erase and Write Page The erase and write application section page, erase and write boot loader section page, and erase and write EEPROM page commands are used to erase one page and then write a loaded flash/EEPROM page buffer into that page in the selected memory space in one atomic operation.
Page 315: Register Description
Atmel AVR XMEGA D 24.13 Register Description Refer to ”Register Description – NVM Controller” on page 22 for a complete register description of the NVM controller. Refer to ”Register Description – PDI Control and Status Registers” on page 292 for a complete register description of the PDI.
Page 316: Peripheral Module Address Map
Atmel AVR XMEGA D 25. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA. All peripherals and modules are not present in all XMEGA devices, refer to device datasheet for the peripherals module address map for a specific device.
Page 317: Instruction Set Summary
Atmel AVR XMEGA D 26. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ← Rd, Rr Add without Carry Rd + Rr Z,C,N,V,S,H ← Rd, Rr Add with Carry Rd + Rr + C Z,C,N,V,S,H ←...
Page 318 Atmel AVR XMEGA D Mnemonics Operands Description Operation Flags #Clocks ← CALL call Subroutine None 3 / 4 ← Subroutine Return STACK None 4 / 5 ← RETI Interrupt Return STACK 4 / 5 ← CPSE Rd,Rr Compare, Skip if Equal...
Page 319 Atmel AVR XMEGA D Mnemonics Operands Description Operation Flags #Clocks ← (1)(2) Rd, -Y Load Indirect and Pre-Decrement Y - 1 None ← ← (1)(2) Rd, Y+q Load Indirect with Displacement (Y + q) None ← (1)(2) Rd, Z Load Indirect None ←...
Page 320 Atmel AVR XMEGA D Mnemonics Operands Description Operation Flags #Clocks ← Z, Rd Load and Toggle RAM location Temp None ← (Z), ← Temp ⊕ (Z) Bit and Bit-test Instructions ← Logical Shift Left Rd(n+1) Rd(n), Z,C,N,V,H ← Rd(0) ←...
Page 321: Datasheet Revision History
Atmel AVR XMEGA D 27. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revisions in this section are referring to the document revision. 27.1 8210C –09/11 Updated all chapters and new figures added according the XMEGA AU manual.
Page 322: Table Of Contents
Atmel AVR XMEGA D Table of Contents About the Manual ..................2 Reading the Manual ..................2 Resources ......................2 Recommended Reading ..................2 Overview ....................3 Block Diagram ....................4 AVR CPU ....................5 Features ......................5 Overview ......................5 Architectural Overview ..................5 ALU - Arithmetic Logic Unit ................6 Program Flow ....................7...
Page 323 Atmel AVR XMEGA D 4.11 I/O Memory Protection ..................21 4.12 Register Description – NVM Controller ............22 4.13 Register Descriptions – Fuses and Lockbits ...........27 4.14 Register Description – Production Signature Row ..........33 4.15 Register Description – General Purpose I/O Memory ........39 4.16...
Page 324 Atmel AVR XMEGA D 6.13 Register Summary - Oscillator .................78 6.14 Register Summary - DFLL32M/DFLL2M ............78 6.15 Oscillator Failure Interrupt Vector Summary ...........78 Power Management and Sleep Modes ..........79 Features ......................79 Overview ......................79 Sleep Modes ....................79 Power Reduction Registers ................81 Minimizing Power Consumption ..............81...
Page 325 Atmel AVR XMEGA D 10.6 Interrupt priority .....................105 10.7 Interrupt vector locations ................107 10.8 Register Description ..................107 10.9 Register Summary ..................109 11 I/O Ports ....................110 11.1 Features ......................110 11.2 Overview ......................110 11.3 I/O Pin Use and Configuration ...............111 11.4 Reading the Pin Value ...................114...
Page 326 Atmel AVR XMEGA D 12.11 Register Description ..................148 12.12 Register Summary ..................158 12.13 Interrupt Vector Summary ................158 13 Hi-Res – High-Resolution Extension ..........159 13.1 Features ......................159 13.2 Overview ......................159 13.3 Register Description ..................160 13.4 Register Summary ..................160 14 AWeX – Advanced Waveform Extension ........... 161 14.1...
Page 327 Atmel AVR XMEGA D 16.12 Register Summary - TWI Master ..............204 16.13 Register Summary - TWI Slave ..............204 16.14 Interrupt Vector Summary ................204 17 SPI – Serial Peripheral Interface ............205 17.1 Features ......................205 17.2 Overview ......................205 17.3 Master Mode ....................206 17.4...
Page 328 Atmel AVR XMEGA D 20.1 Features ......................238 20.2 Overview ......................238 20.3 Operation .......................239 20.4 CRC on Flash memory ..................239 20.5 CRC using the I/O Interface ................240 20.6 Register Description ..................241 20.7 Register Sumary ...................244 21 ADC – Analog-to-Digital Converter ............ 245 21.1...
Page 329 Atmel AVR XMEGA D 22.9 Register Summary ..................280 22.10 Interrupt vector Summary ................280 23 Program and Debug Interface ............. 281 23.1 Features ......................281 23.2 Overview ......................281 23.3 PDI Physical ....................282 23.4 PDI Controller ....................286 23.5 Register Description - PDI Instruction and Addressing Registers ....290 23.6...
Page 330 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL...
Page 331 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Atmel ATXMEGA16D4-CU ATXMEGA16D4-MH ATXMEGA32D4-CU ATXMEGA32D4-MH ATXMEGA128D3-AUR ATXMEGA128D3-MHR ATXMEGA16D4-AUR ATXMEGA16D4-CUR ATXMEGA192D3-AUR ATXMEGA192D3-MHR ATXMEGA256D3-AUR ATXMEGA256D3-MHR ATXMEGA32D4-AUR ATXMEGA32D4-CUR ATXMEGA32D4-MHR ATXMEGA64D3-AUR ATXMEGA64D3-MHR...

Atmel AVR XMEGA D Series Manual

1 About the Manual

2 Overview

3 Avr Cpu

4 Memories

5 Event System

6 System Clock and Clock Options

7 Power Management and Sleep Modes

8 Reset System

9 WDT - Watchdog Timer

10 Interrupts and Programmable Multilevel Interrupt Controller

11 O Ports

12 TC0/1 - 16-Bit Timer/Counter Type 0 and 1

13 Hi-Res - High-Resolution Extension

14 Awex - Advanced Waveform Extension

15 RTC - Real-Time Counter

16 TWI - Two-Wire Interface

17 SPI - Serial Peripheral Interface

18 Usart

19 IRCOM - IR Communication Module

20 CRC - Cyclic Redundancy Check

21 ADC - Analog-To-Digital Converter

22 AC - Analog Comparator

23 Program and Debug Interface

24 Memory Programming

25 Peripheral Module Address Map

26 Instruction Set Summary

27 Datasheet Revision History

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