Atmel AVR XMEGA AU series Manual page 223

–
18.3.4 INTFLAGS
18.3.5 TEMP – Temporary Register
18.3.6 CNTL – Counter Register Low
8331B–AVR–03/12
Interrupt Flag register
Bit 7
+0x03 –
Read/Write R
Initial Value 0
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automati-
cally when the RTC compare match interrupt vector is executed. The flag can also be cleared by
writing a one to its bit location.
• Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically
when the RTC overflow interrupt vector is executed. The flag can also be cleared by writing a
one to its bit location.
Bit 7
+0x04
Read/Write R/W
Initial Value 0
• Bit 7:0 – TEMP[7:0]: Real-Time Counter Temporary Register
This register is used for 16-bit access to the counter value, compare value, and TOP value reg-
isters. The low byte of the 16-bit register is stored here when it is written by the CPU. The high
byte of the 16-bit register is stored when the low byte is read by the CPU. For more details, refer
to "Accessing 16-bit Registers" on page
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT counts positive clock
edges on the prescaled RTC clock. Reading and writing 16-bit values requires special attention.
Refer to "Accessing 16-bit Registers" on page 13
Due to synchronization between the RTC clock and system clock domains, there is a latency of
two RTC clock cycles from updating the register until this has an effect. Application software
needs to check that the SYNCBUSY flag in the
cleared before writing to this register.
Bit 7
+0x08
Read/Write R/W
Initial Value 0
6 5 4
– – –
R R R
0 0 0
6 5 4
TEMP[7:0]
R/W R/W R/W
0 0 0
13.
6 5 4
CNT[7:0]
R/W R/W R/W
0 0 0
Atmel AVR XMEGA AU
3 2 1
– – COMPIF
R R R/W
0 0 0
3 2 1
R/W R/W R/W
0 0 0
for details.
"STATUS – Status register" on page 222
3 2 1
R/W R/W R/W
0 0 0
0
OVFIF INTFLAGS
R/W
0
0
TEMP
R/W
0
is
0
CNTL
R/W
0
223