Atmel AVR XMEGA AU series Manual page 93

8331B–AVR–03/12
• Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor
These bits define the division ratio of the clock prescaler A according to
can be written at run-time to change the frequency of the Clk
.
clock, Clk
SYS
Table 7-2. Prescaler A division factor.
PSADIV[4:0]
00000
00001
00011
00101
00111
01001
01011
01101
01111
10001
10101
10111
11001
11011
11101
11111
• Bit 1:0 – PSBCDIV: Prescaler B and C Division Factors
These bits define the division ratio of the clock prescalers B and C according to
caler B will set the clock frequency for the Clk
will set the clock frequency for the Clk
to Figure 7-5 on page 88
Table 7-3. Prescaler B and C division factors.
PSBCDIV[1:0]
00
01
10
11
Group Configuration
1
2
4
8
16
32
64
128
256
512
PER2
and Clk
PER
fore more details.
Group Configuration
1_1
1_2
4_1
2_2
Atmel AVR XMEGA AU
clock relative to the system
PER4
Description
No division
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Divide by 256
Divide by 512
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
clock relative to the Clk
PER4
clocks relative to the Clk
CPU
Prescaler B division Prescaler C division
No division No division
No division Divide by 2
Divide by 4 No division
Divide by 2 Divide by 2
Table 7-2. These bits
Table 7-3. Pres-
clock. Prescaler C
clock. Refer
PER2
93