Atmel AVR XMEGA AU series Manual page 460

Mnemonics Operands
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
8331B–AVR–03/12
Description
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two's Complement Overflow
Clear Two's Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
Operation
MCU control instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
Atmel AVR XMEGA AU
←
Z 0
←
I 1
←
I 0
←
S 1
←
S 0
←
V 1
←
V 0
←
T 1
←
T 0
←
H 1
←
H 0
Flags #Clocks
Z 1
I 1
I 1
S 1
S 1
V 1
V 1
T 1
T 1
H 1
H 1
None 1
None 1
None 1
None 1
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