Atmel AVR XMEGA AU series Manual page 131

11.7.2 WINCTRL – Window Mode Control register
8331B–AVR–03/12
Table 11-1. Watchdog timeout periods (Continued).
PER[3:0]
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note: Reserved settings will not give any timeout.
• Bit 1 – ENABLE: Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in
to one at the same time. This bit is protected by the configuration change protection mechanism,
For a detailed description, refer to
• Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the
130. When writing a new value to this register, this bit must be written to one at the same time for
the changes to take effect. This bit is protected by the configuration change protection mecha-
nism. For a detailed description, refer to
Bit 7
+0x01 –
Read/Write
R
(unlocked)
Read/Write
R
(locked)
Initial Value
0
(x = fuse)
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in
window mode operation. The typical different closed window periods are found in
Group Configuration
512CLK
1KCLK
2KCLK
4KCLK
8KCLK
"CTRL – Control register" on page 130
"Configuration Change Protection" on page
"Configuration Change Protection" on page
6 5 4
– WPER[3:0]
R R/W R/W
R R R
0 X X
Atmel AVR XMEGA AU
Typical Timeout Periods
0.512s
1.0s
2.0s
4.0s
8.0s
Reserved
Reserved
Reserved
Reserved
Reserved
"CTRL – Control register" on page
3 2 1
WEN
R/W R/W R/W
R R R/W
X X X
must be written
13.
13.
0
WCEN WINCTRL
R/W
R/W
0
Table 11-2.
131