Atmel AVR XMEGA AU series Manual page 332

26.7.2 STATUS – Status register
26.7.3 DATAIN – Data Input Register
8331B–AVR–03/12
Table 26-2. CRC source select (Continued).
SOURCE[3:0] Group configuration
0110 DMACH2
0111 DMACH3
1xxx —
Bit 7
+0x02 –
Read/Write R
Initial Value 0
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – ZERO: Checksum Zero
This flag is set if the CHECKSUM is zero when the CRC generation is complete. It is automati-
cally cleared when a new CRC source is selected.
When running CRC-32 and appending the checksum at the end of the packet (as little endian),
the final checksum shold be 0x2144df1c, and not zero. However, if the checksum is comple-
mented before it is appended (as little endian) to the data, the final result in the checksum
register will be zero.
See the description of CHECKSUM to read out different versions of the CHECKSUM.
• Bit 0 – BUSY: Busy
This flag is read as one when a source configuration is selected and as long as the source is
using the CRC module. If the I/O interface is selected as the source, the flag can be cleared by
writing a one this location. If a DMA channel if selected as the source, the flag is cleared when
the DMA channel transaction is completed or aborted. If flash memory is selected as the source,
the flag is cleared when the CRC generation is completed.
Bit 7
+0x03
Read/Write W W
Initial Value 0
• Bit 7:0 – DATAIN[7:0]
This register is used to store the data for which the CRC checksum is computed. A new CHECK-
SUM is ready one clock cycle after the DATAIN register is written.
Description
DMA controller channel 2
DMA controller channel 3
Reserved for future use
6 5 4
– – –
R R R
0 0 0
6 5 4
DATAIN[7:0]
W W
0 0 0
Atmel AVR XMEGA AU
3 2 1
– – ZERO
R R R
0 0 0
3 2 1
W W W
0 0 0
0
BUSY STATUS
R/W
0
0
DATAIN
W
0
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