Tandy 2000 Service Manual page 77

Tandy@
Model
2000
Service
Manual
7.L.6
Boot ROl,t,/tnterrupt
Controller
(Sheet
7)
7.1.6.1
Boot
ROII{
The
boot
ROM
(Read
OnIy l{emory)
section consists
of
two
ROM
devices.
Device
pinouts
must be compatible
with the
TUIS2532
(Texas
Instruments).
One
of the
ROl4s
provides
CPUDOO -CPUD07
and
the other
provides
CPUDO8 CPUD15. They respond
to all
accesses
in
CPU
(Central
Processing
Unit)
memory
space
from
FC000H
to
FFFFFfI.
The decode
is
done
in
two
stages:
1.
UCS* (Upper memory
Chip
Select, active low
from
F8000H
to
FFFFFH
in
CPU
memory
space)
is qualified with
CPUALE
(CPU Address
Latch Enable,
active high) to provide a
chip
select that is valid
when
all
bus address
bits are valid.
2.
The decoded space
is
then
divided
(by
CPUA14)
into
16K
byte
spaces
so
that it
may
be
shared
with the
character
generator.
7
.L.6.2 Interrupt Controller
The
interrupt controller section consists of
two
Intel
8259A
priority interrupt control devices.
They
are configured
as
slave devices to the
80186
|
s internal
master
interrupt
controller (set for
cascade
mode).
Communication
with the
CPU
occurs
in
one
of
two
forms.
The
CPU
may
write
commands
or
check
status
by accessing
the
space decoded
by
PCS0P6*
(Peripheral
Chip
Select 0, Port 6, active
low
at peripheral
addresses
60H
to
6FH)
for controller 0 or
PCS0P7*
(Peripheral
Chip
Select 0, Port 7, active
low
at peripheral
addresses
70H
to
7FH)
for controller 1.
Address assignments
for
8259A
registers are given in Figure 7-11.
A11
interrupts for
the
Ivlodel 2000
microcomputer
are generated on the rising
edge
of
the interrupt input. If the input is high prior to
the
interrupt, it
must
go low
and remain
low for at least
100
nsec
to insure recognition. If the interrupt level is
unmasked.,
the interrupt controller will then signal the
CpU by
activating the
INT (INTerrupt
output, active high) line.
In
response,
the
CPU
will pulse either
INTAO*
or
INTAI*
(INTerrupt
Acknowledge
0 or 1, active
1ow)
twice.
On
the
second
pulse, the
addressed
controller is
expected
to
place
the vector
corresponding
to the active interrupt
on the
preipheral data bus. Interrupt input
assignments
are given in
Figure 7-11. For
more
information
on programming
and
interfacing with the
8259A,
see
Intel literature.
-
58