Tandy 2000 Service Manual page 262

Tandy@
r{odel
2ggg
Service
l.lanua1
A19,A18
These
two
address
bits are
used
by
the
Model 2ggg
to
decode
which group
of four
256K
bytes (128K
words)
is
being
accessed.
On
the
EXP
ltlEM
BD,
they generate
the signal
SELECT. The
circuit
consists of
U64
(a
74FL38
3-to-8
decoder) used
as a
2-Eo-4
decoder. AI8
and A19
are the
decoded
inputs
and
MC$'
MCl
(89L86
memory
chip
selects
) are the enables.
Three
of the
four
possible
decoded
outputs are provided as jumper
selectable
outputs -
E}1,
82,
and
83.
One
of the jumper options
has
to
be
made
before the
board
will operate.
For
the first
board
in
the
system,
the jumper must be
beLween
Bl and S; for the
second
board
between
82
and
S,
and
for the third
board
between
83
and
S.
See
Figure 9-2 for
more
details.
A17
This
address
bit is
cornbined
with the
RAlr{
row address strobe
RASP
to select either the array high
word (AI7
true) or
the
array low word
(A17
false). This takes place at
U15.
A16
thru
A1
These address
bits are
used
by
the
RAIt'l
ICs
to
decode one
of
64K
internal
memory
locations.
The
RAIvI
ICs,
due
to the
number
of
pins, require the
address
bits to
be
divided into
two groups
and
the
groups loaded
sequentially.
These
two groups are
ROW
address (loaded first)
and
COLUMN
address (loaded
second).
The
circuit that
accomplishes
this is
composed
of line
receivers
U68,
u7g (74L5244s) r and
2-to-l- multiplexers
U67 and
u69
(748258s).
The
line receivers are
always
enabled.
The
multiplexers are
enabled when
ENRCAD*
is true (low).
The
address group
applied to the
RAMs
is
determined
by
the logic
Ievel of MUX* low
(normal state) for
row address,
high (active
state) for
column
address.
The
outputs of the
decoders are
routed to the
RAll
array
through
damping
resistors (RP4).
These
resistors are
shared
by refersh
address
buffer
U56.
9.2.3
Refresh
Address
The 256
refresh
address combinations
are generated
by
an
eight-bit
counter
V72.
The
clock for this
counter
is
RFCNT*
which occurs
at the
end
of
each
refresh cycle.
The counter
works
in the continuous
mode,
i.e. the
counter counts F, 1,
..254, 255, fr,..etc.
The
refresh
address
buffer
U66
applies
ttte
current count
to the array via the
damping
resistors
RP4
when
it
is
enabled
by
ENRFAD*
being
true (low)
(ENRCAD
will
be
false).
253