Tandy 2000 Service Manual page 647

CHAR HORIZ PERIOD
VERT
SYNC WIOTH
PIN CONFIGURATI(JN
REG
TAELE START
REGISTEF
AUXILIARY AOORESS
REtiISTER
2
AUXILIARY ADDRESS
REGISTER
I
ATTRIBUTE
LATCH
INTERNAL BUS
14
BIT ADORESS
ROW TABLE POINTER
REGISTER
INTERNAL VIDEO
ADDRESS REGISTEF
TIMING
AND
CONTROL
VD7-
O
CSYNC
LPSTE
REGISTER
SELECT
SL3 DMAR VBTANK
SLz
WBEN CSYNC
FIGURE 1: CRT 9007
BLOCK
DIAGRAM
DESCRIPTION OF PIN FUNCTIONS
PROCESSOR
INTERFACE:
PIN
NO.
NAME SYMBOL
FUNCTION
7,5,4,
2, 39,
37,
1
0, 9, 8,
6,
3, 1, 38, 36
Video Address
13-0
VA13.VAO
These
14
signals
are
the binary address presented
to
the video memory
by
the CRT 9007.
The function depends on the partrcular CRT 9007 mode
of
operation. VA13-6 are outputs
only. VA5-0 are bidirectional.
-Double
Row Buffer
Conf
iguration:
VA13-0 are active outputs for
the DMA operations and are
in
their high impedance state at
all
other times,
-Single
Row Buffer Configuration:
VAi3-0
are actlve outputs during the first scan line
of
each data row and are in their high
impedance state at all
other times.
-Repetitive
Memory Addressing Configuration
:
VA13-0
are active outputs
at
ai-l
times except during horizontal and
vertical retrace
at
which
time they are in
their high impedance
state"
lf
row
table addressing is
used for either single row buffer or repetitive memory addressing
modes, VA13-0
are active outputs during the horizontal retrace
at
each data row boundary to
allow the CRT 9007 to retneve the row table address. For
processor read write operatlons
VA5-0 are inputs that select the appropriate internal register.
16,17,18,19,
20,22,23,24
Video Data 7-0 VDT.VDO
Bidirectional video data
bus:rlqring processor Read,write operations data is transferred via
VD7-VqO when chip strobe (CS)
is
active. These lines are
in
their high impedance state
when
eS
ls
inactive. During CRT 9007 DMA operations, data from video memory
is
input vra
VD7-VDO when a
new
row
table address
is
being retrieved or when the attribute latch is being
updated in
the attrrbute assemble mode.
VD7-VDO
are outputs when the external row buffer
is
updated with
a
new attribute in
the attribute assemble mode.
25 Chip strobe
m
Input;this signal when active low,
allowsthe processorto read orwrite internal CRT9007
registers. When reading from an internal CRT€007
register, the chip strobe (CS) enables the
output drivers. When writing
to
an internal CRT 9007 register, the trailing edge of this signal
latches the incoming data. Figure
2
shows all processor read/write timing.
26
Reset RST Inout: this active low
siqnal puts the CRT 9007 into
a
known, inactive state and insures
tnbt the horizontal synC(FiS)
output is inaclive. Activating this input has the same etfect as
a
RESET command. After initialization,
a
START command causes normal CRT 9007 opera-
tion.
See
processor addressable registers seclion, Register
16
for
the reset state definition.
27 Interrupt INT
Output;an
interrupt
to
the processor from the CRT 9007 occurs when this signal
is
active
high. The interrupt returns to
its
inactive
low
state when the status register is read.
252