Tandy 2000 Service Manual page 517

intel
iAPX
186
This input
m
ust
satisf
y
set-u
p
and hold times
to
guarantee
proper operation of the
circu
it"
In addition, the iAPX
186,
as part of the integrated
chip-select logic,
has
the capability to program
WAIT
states
for memory
and
peripheral blocks. This
is
dis-
cussed in
the Chip Select/Ready Logic description.
RESET Logic
The IAPX 186 provides both a
RES
input pin and
a
synchronized RESET
pin for
use
with other
system
components. The RES
input pin on the iAPX
1BG
is
provided
with
hysteresis in
order to facilitate power-
on
Reset
generation via an RC network. RESET
is
guaranteed
to
remain
active for at least
f
ive clocks
given a
RfS
input of at
least
six clocks. RESET may
be
delayed
u
p to two
and one-half clocks
behind
RES
Multiple iAPX
186
processors may be synchronized
through the
RES
input pin, since this input
resets
both the processor and divide-by-two internal count-
er
in
the clock generator. In order to insure that
the
d
ivide-by-two
cou
nters
all
beg
in
gg1rrting
at
the
Same trme,
the active going edge of
RES
must satisfy
a 25 ns
setup
time before the falling edge
of
the
B01BG
clock input. In
addition, in order
to
insure
that
all CPUs
begin executing
in
the same clock
cycle,
the
reset must satisfy a25 ns setup
time before the rising
edge
of the
CLKOUT
srgnal
of
all
the processors.
LOCAL BUS CONTROLLER
The |APX 186 provides
a
local bus controller
to
generate the local bus control signals.
In
addition,
it
employs
a
HOLD/HLDA
protocol
for
relinquishing
the local
bus
to other bus
masters.
lt also
provides
control lines that can be used
to
enable external
buffers and to direct the flow of data on and off
the
local
bus.
Memo ry
lPeripheral Control
The IAPX
186
provides ALE,
RD,
and WH bus
control
signals. The RD and
Wn
signals are used
to
strobe
data
from memory to the iAPX
186
or to strobe
data
f
rom
the iAPX
186
to
memory.
The ALE line provides
a strobe
to
address latches
for the
multiplexed
ad-
dress/data
bus. The |APX 186 local bus controller
does not provide a
memorylTO signal.
lf this is
re-
quired, the user will
have
to
use
the 32 signal (which
will require external latching),
make
the memory and
UO
spaces nonoverlapping,
or
use
on
ly the
in-
teg
rated chip-select circu itry.
Transceiver Control
The iAPX
1
86 generates two control
sig
nals
to
be
connected to
B2BG
B2B7
transceiver chips. This capa-
bility
allows
the
add
ition of
transceivers
for
extra
buffering without adding external
logic
These con-
trol
lines, DT
R
and
ffi,
are
generated to control the
flow of data through the transcetvers. The operation
of
these
signals is shown in
Table
6.
Table
6. Transceiver Control Signals Description
Name
Function
Enable)
Enables
the output drivers
of
the transceivers.
lt is
active
LOW
during memory,
I
O,
or
INTA
cyc les"
DT R
(Data
Transm
tt
Re ce
ive)
Determines
the direction
of
travel
th
rough the transceivers
r
--
|
.ot
du
ring a read operation
u
aot during
Local Bus Arbitration
The iAPX
186 uses a
HOLD/HLDA system
of local bus
exchange.
This provides an asynchronous bus
ex-
change mechanism. This means multiple
masters
utilizing the
same
bus can operate at separate clock
f
requencies. The iAPX 186 provides
a
single
HOLD/HLDA
pair through which all other bus
mas-
ters
may
gain control of the local bus. This requires
external circurtry
to
arbitrate which external device
will gain control of the bus from the iAPX
186 when
there is more than one alternate local bus
master.
When
the |APX
186
relinquishes
control of the local
bus,
it
floats
DEN,
ilD,
WR, S0-S2,
meR,
ADO-
AD15, ,A16-A19, BEE, and DT/R
to
allow
another
master
to drive these lines directly.
The iAPX 186 HOLD latency time,
i.e.,
the time
be-
tween HOLD request and HOLD acknowledge, is
a
function
of
the activity occurring in the
processor
when the HOLD request is received. A HOLD request
is
the
highest-priority activity request which the
pro-
cessor may receive: higher
than instruction fetching
or internal
DMA
cycles. However, if a DMA cycle is
in
p
rog
ress,
the
iAPX
1
86
will
com
plete
the
transf
er
before relinquishing
the
bus.
This implies that
if
a
HOLD request
is
received
just as a
DMA transfer
begins,
the HOLD latency time can be
as
great as
4
bus cycles. This
will occur if a
DMA
word transfer
operation is taki.ng place from an odd
address
to
an
odd address. This is a total of 16 clocks or more,
if
WAIT
states
are
required. In
addition, if locked
trans-
fers are performed, the
HOLD latency
time will
be
increased by
the length of the locked
transfer.
(Data
14
AFN.02217C