Tandy 2000 Service Manual page 107

TandlP Model
2000
Service
Manual
7.I.1I.3
RS-232
Operation
(page
13)
For
asynchronous RS-232 operation, the
baud
rate crock for
both
transmit
and
receive is derived
from
the
9253-5
clock
1
output.
To selecL the internally derived clock
(externar
synchronous
operation is outlined below), port
00H
bit. I is
set to rtlrr. This routes the
8253-5
clock l output to
both
the transmit
and
receive clock inputs
on
the gzsra.
Bit.
assignments
for port
OOH
are
shown
in
Tab1e
7-5.
B
it
As
s
i gnrnent
O
KBEN
I
EXTCLK
2
SPKRGATE
3
SPKRDATA
4
RFSHEN
5
FDCRESET*
5
TMRINO
7
TMRINI
Funct
ion
Keyboard
Enable
External
baud
rate
clock
Enable
periodic
speaker output
Direct output to
speaker
Enable
refresh
and baud rate
clocks
Reset
827
2
Enab
Ie
8
0I8
5
t
imer
0
Enable 80186
timer I
Active
Level
active
high
active
high
active
high
active high
active
low
active high
active
high
arg
fr0tt
o
NOTE: Following
a reset, all bits at port
00H
Table
7-5. port
00H
Bit
Assignments
Inputs for the
8251A
are
taken from
,J1
after
being level-shifted
from
+12
vdc levels
and
inverted by
7514g9
interfice
chips.
These
inputs include: receive data, crear to
send,
and
data
set
ready (a11
active row). outputs
from
the
g25lA which are
inverted
and
leveI-shifted to
+12
vdc are: transmit
data,
request to
sendr
and
data terminal ready (all active low).
Tleo
active high outputs
RxRDY
and
TxRDY)
aie
ORed
together to
form
sERrNT02
(sERial rNTerrupt
controlrer 0, level zl.
RxRDy goes
active high
when
a full character is received. This bit ii
reset
by a read to the data port.
rn a simirar
manner,
TxEl4p goes
active high
when
the transmit buffer is
empty
whire
the
transmitter is
enabled
or
remains
active
trigh while
the
transmitter is disabred. rt is reset by a write to the
g25lA
data port if the transmitter is
enabled-.
synchronous
operation is identical to
asynchronous operation
except
that the transmit
and
receive clocks are supplied by
the
remote
device. Like the data interface,
these clocks
are
level-shifted
by
the
75L489
inverting buffers.
To
route
the
externar clocks to the
8251A,
port
00H
bit r
must be
set to
,,1u.
98