Tandy 2000 Service Manual page 69

Tandy@
Model
2000
Service
Manual
7
.L.4.1
VIDEO
SYSTEI*I THEORY
OF
OPERATION
The
CPU
may
access
the
CRT9007
registers
by
driving
PCS2*
active Iow.
A
PAL10L8
conditions
PCS2*
with
CPUAOO
and
CPUDEG*
to
generate
a chip select to the
VPAC
on
even
addresses
only while data is valid.
The
PCS2*
signal is
also
conditioned
with
CPUBHE*, CPUDEN*'
and
CPUIOW*
to
generate
the
ADDLWE*
(ADDress Latch
Write
Enable)
signal
on
odd
addresses.
Data from
CPUDO8-CPUDI5
is written to
the
address
latch
on
the rising
edge
of
ADDLWE*'
approximately
30 nsec
after the rising
edge
of
CPUIOW*
(the
propagation
delay through the
PAL10I8
).
The
logic allows writing to
both
the
9007 and
the
address
control register at the
same
time.
Data and addresses
are buffered
through
74F
series octal
buffers with control signals generated
in the
PAL10L8.
The
data buffer, a
74F245,
is
enabled
when
either
VIDCS*
(the
VPAC
chip select) is active
1ow,
or
both
VIDHOLD
and
VIDHLDA
are active high, indicating a
CRT9007 Dl'lA
cycle is in
progress.
When PCS2*
is active, the data buffer's direction
is controlled by
CPUA06.
When
low, data is transferred
from
the
CPU
to the
CRT9007; when
high, data is transferred
from
the
CRT9007
to the
CPU
on
data lines
CPUD00-CPUDO7.
During
a
VPAC
DltA
cycle, the data buffer is
enabled
with
the
transfer direction
from
the data
bus
to the
CRT9007.
VAO0-VA05
are bidirectional
address
lines
and
are
buffered
through
a
7
4F245 whose
enable
signal is derived
from
PCS2*
active
low
or
VIDHOLD
and
VIDHLDA
active high. Direction
for the
74F245
as
well as the
74F244
enable (buffering
VA07-VA13)
is
generated from
the
HIP (HoId
In
Progress'
active high
when
VIDHOLD
and
VIDHLDA
are active) signal.
Addresses
are transferred to the
CRT9007
when
HIP
is
low.
A11
DIIA
cycle timing is derived
from
VIDCCLK*
(the
VIDeo
Character CLocK), which
in turn is derived
from
VIDDCLK
(the
VIDeo
Dot
CLocK). Bit 5 in the
address
control register
selects
how many
dot clocks constitute a character
clock
(hence the
number
of dots
across
a character, either 8
or
I0).
In the
10
dot-per-character
mode,
the counter is initialized
with a value of 06H.
When
the
counter counts up
to a
value
of,
OAH,
a'0'is
clocked
LnLo
L/2 of a
74574
flip flop
on
the next rising dot clock
edge,
forcing the
VIDLDSH (VIDeo
LoaD,/SHift)
signal low for
use
by the CRI902L.
The
inverted
value of the counterrs
Qc
output
(delayed by four
745 gate
delays
to
make
it coincident with
VIDLDSH)
is
used
to
generate VIDCCLK*.
When
a
count
of
OAH
is
decoded,
a
"0n
is
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