Tandy 2000 Service Manual page 652

Repetitive Memory Addressing Operation
In
this operation mode, the CRT 9007 wilf repeat
the
sequence of video addresses for every scan line of every
data row. The CRT 9007 address bus will enter its
high
impedance state during all horizontal retrace intervals
(except
the retrace interval at
a data row boundary if the
CRT 9007
is
configured
in
a row driven addressing mode).
This arrangement allows for such low end contention
schemes as retrace intervention (the processor is only
allowed access
to video memory during retrace intervals)
and processor priority (the processor has an unlimited
access
to video memory). A high end contention scheme
can
be
employed which
uses
a
double speed memory
such
that
in a
single character period
both the
processor
and
the
CRT
9007 are permitted access to video memory at pre-
determined
time slots. Figure
11 illustrates the CRT 9007
configured with
a
double speed memory. Typical timing for
this mode is
illustrated
in
figure
12.
3X
DRIVER
INT
RST
+
5V
GNO
TsT
re
vrtl"6
cRT
9o,c7
V
PACIU
G
VD/,6
SL3.SLg
CUNS
CBLANX
VIDEO
RAM
3X BIDIRECTIONAL
DR
IVER
VIDEO
ADDRESS
VIDEO
DATA
VDC LD/SH
R3'RO
CURSOR
RETEL
ATTRIEUTES
cRT
Boo2
vsYNc
VDAC'M
CH
ARACTE
R/ATTRIBUTES
t^t.fr
GENERATOR
VIOEO
CftR
TO MONITOR
,t
ffi
DCLK
CCLK
T1
r2
VIDEO
RAM
ADDRESS
SSOR
FIGURE
11
:
CRT
9007 CONFIGURATION WITH DOUBLE SPEED
MEilORY
u.t
TSC
vA13-0
VD7,O
FIGURE 12: GRT 9007 REPETITIVE MEMORY ADDRESS
TlillNG
(32 CHARACTERS PER
DATA
ROW)
257