Tandy 2000 Service Manual page 524

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Mr
DESTINATION
ro DEc
lNc
!t
ro
SOURCE
DEC
INC
TC INT
SYN
P
T
D
R
o
x
CHG/
NOCHG
ST]
STOP
B,
w
X
DON'T
CARE.
DMA Channel Control Word Register
Each DMA Channel Control word
determines
the
mode
of
operation
for the
particu lar 80180
DMA
channel. This register specifies:
o
the mode of synchronization;
.
whether bytes or words will be transferred;
o
whether interrupts will be generated after the
last
transfer;
o whether
DMA
activity
will
cease
afte
r a
pro-
grammed number of
DMA cycles;
o the
relative
priority of
the
DMA channel with
respect
to the other
DMA channel;
o
whether the source pointer
will
be incremented,
decremented,
or
maintained constant after
each
transfer;
o
whether the source pointer addresses memory
or
l/O space;
o whether the
destination pointer will
be
incre-
mented, decremented, or maintained constant
af-
ter each transfer:
and
o
whether
the
destrnation
pointer will
address
memory
or l/O
space.
The DMA channel control registers
may be changed
while the channel is
operating.
However,
any
changes made
du
ring operation will
af
f
ect the
cu r-
rent DMA
transfer.
DMA Control Word Bit Descriptions
Figure
18.
DMA Controf Register
INT:
TC:
SYN:
(2 bits)
SOU
RCE:lNC
M/to
DEC
DEST:
INC
M/to
DEC
Enable Interrupts to
CPU
on
Trans-
f
er
Cou
nt
term
ination.
lf
set, DMA
will terminate when
the
contents
of the
Transfer Count
reg-
ister reach
zero.
The
ST
STOP bit
will also be reset
at
this
point
if TC
is
set.
lf
this bit is
cleared, the
DMA
unit
will
decrement
the
transfer
count register for each
DMA
cycle,
but the
DMA transfer
will not
stop
when the contents of the
TC
reglster
reach zero.
00
No
synch
ron
ization.
NOTE: The
ST
bit
will
be cleared
automatically when the contents
of the TC register
reach zero
re-
gardless of the state of
the TC bit.
01
So
u
rce
sy
n c h
ron
izatio
n
.
1
0
Destination synchronization.
1
1
Unused.
lncrement source pointer by
1
or
2
(depends on BIW) after
each
transf
er.
Sou
rce pointer is
in
M/lO
space
(1/0)
Decrement source
pointer by
1 or
2
(depends on
BIW)
after
each
transfer.
Increment destination pointer by
1
or 2 (ElW) after each
transfer.
Destination
pointer
is
in
M,ilO space
(1l0)
Decrement destination
pointer by
1
or
2 (depending on BIW) after
each
transfer.
Channel
priority-relative to
other
chan
ne
l.
0
low priority.
t
high priority.
Chan
nels
will
alternate cycles
if
both set at same priority
level.
B/W:
ST/S-TOP:
Byte/Word
(011
) Transfers.
Start/stop
(1
/0) Channel.
Change"Do
not
change
(110)
sT/sTOP bit.
lf
this bit is set
when
writing
to the
control word,
the
STIS-TOP
bit will
be
programmed
by
the write to the control word. lf this
bit is cleared when writing the
con-
trol
word, the
ST,'S-TOP
bit will
not
be altered.
This
bit
is not stored;
it
will
always be a 0 on
read.
CHG/NOCHG:
21
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