Tandy 2000 Service Manual page 265

Tandy@
Model
2000
Service
l{anua1
9.2.5
Timing
Sequence
Generator
The
timing
sequence
generator
consists of delay lines
V32
|
V49,
half the J-K flip-flop
U48' and
the
AND-OR
gate
V47.
The
timing
sequence
is started by triggering the flip-flop
by the leading
edge
of the signal
It{EllCYc.
This sets
Q
1ow.
This
low appears 80
nanoseconds
later
from
the delay line at
the clear of the flip-flop
and
sets
Q
high. Thus'
an
80
nanosecond
negative pulse is initiated
down
the delay line,
creating a series of timing pulses once. If
the
-conditions
are rightr
EI
short pulse
RFSRT
is
created
at
the
300 nanosecond
tap to
begin
the cycle
over.
The
signal
I{TEMCYC/
is
created under two
conditions.
The
first is
a
memory
access
- that is,
SELECT, I{READ
and
I\{WRITE
are true.
The second
condition is the
need
for a refresh cycle. If
SCNT
is true but
SELECT
is false, the next
MREAD
or
IvIWRITE
creates a
t'lEIvlCYC.
The
signal
RFSRT
will
add
cycles to
the
original cycle if
and
only if
SELECT
is true
and
as long
as
SCNT
is true.
These added
cycles are refresh cycles
and
can
be
added
only if the signal
BUSARDY
(cPU
"wait") can
be
controlled.
9.2.6
Refresh
Counter
The
refresh
method
is basically a single cycle
every
16
microseconds.
The
exception
is that the refresh cycles
are
allowed
to stack
up
until a
convenient time
when
a refresh
burst
occurs
that is
equal
in
number
to the deficit
amount.
The
refresh
counter circuitry consists of the refresh period
counter U45, U61,
and
the deficit
counter V27, Ull,
and L/6
of U46.
The
refresh
counters
U45
and
U61
provide a
constant
time tick (L25
nanosecond
negative
pulse ) every
15.0
microseconds Eo
U27. This
causes
U27
to
count
up.
Every
time a refresh cycle is
performed,
a signal
RFCNT
is
applied
which causes
V27
to
count
down.
The
CNT
logic UIl
samples
the output of
V27
and, if the count is greater than
zero,
CNT
is true.
9.2.7
Refresh Count Synchronizer
The
output signal from the refresh counter
CNT
needs
to
be
synchronized
with
MREAD
or
IIIWRITE
to prevent
CNT
from
affecting the
access
status after the cycle
has
started
(RDY
already set). This is
accomplished
by the two flip-flops
-255-