Tandy 2000 Service Manual page 597

int€l'
9253/8253-5
OPERATIONAL
DESCRI PTION
General
The
c,ilmplete
f
lt
nctional
def in
itior-r
of the 8253
is
prog
ram
med by
the
systems
sof
tware.
A
set
of
control
words
m
ust be sent out by the
CPU
to
rn
itialize
each
counter of the
8253
with the desired MODE
and quanttty
inf
ormation. Prior
to initialization, the
MODE, Count, and
output
of all counters is
undef ined. These
control words
program
the
MODE,
Loading sequence and
selection
of
binary
or
BCD
counting.
Once programmed, the 8253
is ready
to perform whatever
trmrng tasks
it
is assigned
to
accomplish
The actual cotlnting operation
of
each counter
is
completely
independent and
additional logic is provided
on-chip so that the uslral problems associated
with
ef
f
icient
mon
itoring and
management
of
external,
asy
nch
ronous events
or
rates
to
the
m
icrocomputer
system have been
eliminated.
Programming the
8253
All of the MODES for each
coutnter are
prograRlnred by
the
systems
sof
tware by
srnr
ple
|
,'O
operations
Each
counter uf the
8253 rs
tndtvtdrtally
prograrTrmerl
Dy
wrrting
a
contrrtl worrJ
into the Control
Worrl
Feqtster
{A0 Al
11l
Control Word Format
D7 D6 D5
Da
D3
D2
Ds
SC1 SCO
R L1
RLO M2 M1 MO
BCD
Definition of Control
SC
Select Counten
SC
1
SCO
RL
-
Read/Load:
R
L1
R
LO
Counter Latching
operation
{see
R
EAD
'WR
ITE
ProcecJure Sectiorr)
0
I
R
eari Loacl rnost
sign if ica
nt byte
on
ly.
M
MO DE:
M2 M1
MO
Mode
0
Mode
1
Mocle
?
Mode
3
Moci
e
4
MocJ e
BC D:
0
Binarv Courrter
1
6-bits
1
Binary
Cocled
Decimal (BCD)
Counter
(4
Decades)
Counter Loading
The
count register is not loaded until the
count value'is
written (one
or two
bytes, depending
on the
rnade
selected by
the
RL
bits),
followed
by
a
rising
edge and
a
falling
edge
of the clock. Any read
of the counter prior
to
that falling clock
edge may
yield invalid
data.
MODE Definition
MODE
0:
Interrupt on Terminal Count. The
output
','t'ill
be
initially low after the
mode
set operation.
After
the
count is loaded into the selected
cou
nt register, the
out-
put will
remain low and
the counter
will count. When
ter-
minal
count is
reached
the output will go high and
re-
main high
until the selected count register is
releaded
with the mode or a new count
is
loadeci.
The
counter
continues
to
decrement
after terminal
clrunt has
been
reac
h
ed.
Rewriting a Counter
register during counting
rcsults
in
the
f
ollowing:
{1)
Write 1st
byte stops the current countinE.
(21
Write 2nd byte
starts the new
count"
MODE
1:
Programmable One-Shot.
The
outpi,t wtll
go
low
on
the count
followrng the rising
edge
of
th;
gate
ln-
put
The
output
will go high on the terminal count.
lf
a new
count
value
is
loaded
while
the
output
is low it wtll
not
affect the duration of the
one-shot
pulse until the
suc-
ceeding
trigger.The current count can be read
at
any
time without affecting the one-shot pulse.
The
one-shot
is retriggerable, hence lfre
cutput wtli
re-
main low
for the full count after
any
rising
edge
of
the
gate
in
put.
Reacl
/Loaci
least
signif
icarrt
byte
orrly.
R ea
rJ
Loari
lea
st
s
ign
if
ica
nt [ryte
f
ir st
,
then most significant
bYte.
D1
0
1
1
0
0
Se
lect
Cou
nter
0
0
1
Se
I
e
ct
Cou
nter
1
1
0
Select
Counter
?
1
1
I
lleqa
I
6-142
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