Tandy 2000 Service Manual page 506

iru
|APX
186
Table
1.
80186
Pin Description (Continued)
Symbol
TES
Pin
No.
47
Type
I
Name and
Fulctiln
T-EST
is examined by the WAIT instruction.
lf
the
T=EST
input
il
I!qH
when
"WAlT" execution begins,
instruction
execution
will
suspend.
TEST
will
be
resampled until it goes
LOW at
which time execution will
resume.
lf interrupts
are
enabled while
the 80186
is
waiting
for TEST,
interrupts will
be
serviced.
This
input is synchronized
internally.
TMR IN
O
TMR
IN1
20
21
I
Timer Inputs are
used
"'tl-t;;ay.Locr.
;.;";,rotr,g"r'r
d;;"rrdrg
,pon
the
programmed timer
mode. These
inputs are active
HIGH
(or
LOW-Io-HIGH
transitions
are
counted) and internally
synchronized,
TMR
OUT
O
TMR OUT
1
22
23
o
o
Timer outputs
are used
to provide single pulse
or continuous waveform
gener-
ation, depending upon the timer mode selected.
DRQO
DRQl
1B
19
I
I
DMA Request is driven HIGH b;;;
"-,"*
O"rt." when ,, O* that
a
DMA channel (Channel 0
or
1)
perform
a transfer. These signals are active
HIGH,
level-triggered, and internally
synchronized.
NMI 46
Non-Maskable
Interrupt is an
edge-triggered
input which
causes
a type
2
interrupt
NMI
is not
maskable
internally A transition from a
LOW
to
HIGH
initiates the interrupt at the next instruction
boundary. NMI
is latched
inter-
nally.An
NMI
duration of
one
clock or
more
will guarantee
service. This
input
is
i
nternally
synchronr zed.
INTO, INT1,
lNT2rlf114g
lNT3/
lr.lTAl
45,44
42
41
I
I'O
I'O
Maskable Interrupt Requests can be requested
by
strobing
one of these
pins.
When configured
as
inputs, these pins
are
active HIGH.
Interrupt
Requests are
synchronized internally.
lNT2
and
lNT3 may
be
configured
via
software to
provide active-LOW interrupt-acknowledge output
signals. All interrupt inputs
may be conf
igured
via software to
be
either edge- or level-triggered.
To
ensure
recognition, all interrupt requests must remain active until the interrupt
is
acknowleged.
When iRMX mode is
selected,
the function of these
pins
changes (see
Interrupt Controller section
of this
data sheet).
A19/56,
A18,/55,
A17/S4,
A16/53
65
66
67
68
o
o
o
o
Address
Bus
Outputs (16-19) and
Bus Cycle Status
(3-6)
reflect the
four
most
significant address bits during
T1
.
These signals are active
HIGH.
During
T2,
T3, Tyy, and T4, status information
is
available on these lines as
encoded
below:
Low
High
S6
Processor
Cyc
le
DMA
Cycle
53,S4,
and 55
are
def
ined
as
LOVV
during
T2
-Ta
AD1 5_ADO
't
0-17,
1-8
r/o
Address/Data Bus
(0-15) signals constrtute
the time mutiplexed memory or
l/O
address (Tr ) and data (T2, T3,
T1ry,
and T+) bus. The bus is
active
HIGH. ,46
is
analogous
to
BHE
for the lower byte of the data bus, pins Dz
through
D6.lt
is
LOW
during
T1 when
a
byte is
to
be
transferred
onto the lower
portion of
the
bus in
memory or l/O operations.
BHETST 64
o
During
T1
the Bus High Enable signal should be used to determine if data
is
to
be enabled onto the most
significant
half of the data
bus,pins
D1 s-DA.
AHE
is
LOW
during
T1
for
read,
write, and interrupt acknowledge
cycles when
a
byte
is
to
be
transferred
on
the
higher half of the
bus. The
57 status information
is
available durin gTz,
T3, and
T+ Sz
is
logically equivalent to BHf
.
The signal
is
active LOW and is tristated
OFF
during bus
HOLD.
EHE and A0 Encodings
BHE Value A0 Value Function
o
0
1
1
0
1
0
1
Word
Transfer
Byte Transfer on upper half
of
data bus (D15-D8)
Byte Transfer on lower half of
data
bus (Dz-Do)
Reserved
AFN-02217C