Tandy 2000 Service Manual page 528

iru
|APX
186
ALT:
The ALT bit determines which of two
MAX
COUNT
registers is used for count comparison.
lf
ALT
:
0,
register
A
for that timer
is
always used, while if
ALT
:
1,
the comparison will alternate between register
A
and register B when each maximum count
is
reached. This alternation allows the user to change
one
MAX CoUNT
register while the qther
is
being
used, and thus provides
a
method of generating non-
repetitive waveforms. Square waves
and pulse out-
puts
of
any duty cycle are
a
subset
of
available
signals obtained by not changing the final
count
registers. The
ALT
bit also determines the
f
unction of
the
timer output pin. lf
ALT
is
zero, the output pin will
go Low
for one clock, the clock after the maximum
count is
reached.
lf
ALT
is
one,
the output pin
will
ref
lect the current MAX
COUNT
register being
used
(Ol1
for
BIA).
CONT:
Setting the
CONT
bit
causes
the associated timer
to
run continuously, while resetting it
causes the timer
to halt upon
maximum count. lf
CONT-0
and
ALT
:1,
the
timer will count to the MAX COUNTregister
A
value, reset, count to the register
B
value, reset,
and
h
alt.
EXT:
The external bit selects between internal and
exter-
nal
clocking for
the timer. The external signal may
be
asynch
ronous with respect to the
80186 clock. lf this
bit is
set, the timer
will count
LoW-to-HIGH trans-
itions on the input pin.
lf
cleared,
it will
count
an
internal clock while using the input pin for control.
In
this
mode, the
f
unction of the external pin
is defined
by
the
RTG
bit. The maximum input to
output transi-
tion
latency
time
may be as
much as
6
clocks.
However,
clock inputs
may
be pipelined as
closely
together as every
4
clocks without losing
clock
p u lses.
P:
The prescaler
bit is ignored unless internal clocking
has been selected (EXT
-
0).
lf the
P
bit
is
a
zero, the
timer will count
at
one-fourth the internal
CPU
clock
rate.
lf the
P
bit
is
a one,
the output of timer
2
will
be
used
as a
clock
for the
timer. Note that the user must
initialize and start timer 2
to
obtain the prescaled
c
loc
k.
RTG:
Retrigger bit
is
only active
for internal clocking
(EXT
-0).
In
this case it determines the control function
provided by the input
pin.
lf
RTG -
0,
the input level gates the internal clock
on
and off. lf
the input pin
is HIGH, the timer
willcount;
if
the input pin is
LOW the
timer will hold
its value.
As
indicated previously, the input signal may be
asyn-
chronous with respect to the
80186
clock.
When RTG
-
1,
the input pin detects
LOW-Io-HIGH
transitions. The
first such transition starts
the
timer
running, clearing the timer value to
zero on the
first
clock, and then incrementing thereafter.
Further
transitions on the input pin will again
reset the
timer
to zero, from which it will start counting up again.
lf
CONT
-
0, when the timer has reached maximum
count, the EN bit
will
be cleared, inhibiting further
timer activity.
EN:
The
enable bit provides programmer control over the
timer's
RUN/HALT status. When set,
the timer is
en-
abled
to
increment subject
to the
input pin
con-
straints
in the
internal clock mode
(discussed
previously).When cleared, the
timer will
be
inhibited
from counting. All input pin transitions during
the
time
EN
is zero
will
be ignored.
lf
CONT is
zero, the
EN
bit is
automatically cleared upon maximum
cou nt.
INH:
The inhibit bit
allows
for
selective updating
of
the
enable (EN) bit. lf INH
is a one
during the write to the
mode/control word, then the state of the
EN
bit will
be
modified by the write. lf
INH is
a zero during
the
write, the
EN
bit will be unaffected
by
the operation.
This bit
is not stored; it
will always
be a 0
on a
read.
INT:
When set,
the
INT
bit enables interrupts from the
timer, which
will
be generated on every
terminal
count. lf the
timer
is
configured
in dual MAX
COUNT
register mode, an interrupt will
be generated
each
time the value in
MAX
COUNT
register A is
reached,
and each time the value in
MAX COUNTregister B
is
reached.
lf
this enable bit is cleared after the
inter-
rupt request
has been
generated, but before a pend-
ing interrupt is
serviced,
the interrupt
request will
stlll be in
force. (The request is latched in the
Inter-
rupt
Controller.)
MC:
The Maximum Count bit
is set whenever the timer
reaches its
f
inal maximum count value. lf the
timer
is
configured in dual MAX
COUNT
register mode, this
bit will be set each time the value in
MAX
COUNT
register A
is
reached, and each
time the value in
MAX
COUNT
register B is reached. This bit is set
regard-
less
of the
timer's interrupt-enable bit. The MC bit
gives
the
user the ability
to
monitor timer
status
th roug
h
software instead of
th
roug
h
interru pts.
Programmer intervention
is
required to
clear this
b
it.
25
AFN-02217C