Tandy 2000 Service Manual page 646

9FJ'ff$'7
H
FEATURES
!
Fully Programmable Display
Format
Characters per Data Row (8-240)
Data Rows per Frame (2-256)
Raster Scans per Data Row
(1-32)
n
Programmable Monitor Sync Format
Raster Scans/Frame (4-2048)
Front Porch
-
Horizontal (Negative
or
Pos
itive)
-
Vertical
Sync Width
-
Horizontal
(1-128 Character
Times)
- Vertical (2-256 Scan Lines)
Back Porch
-
Horizontal
n
oi
rect
output#StA';1"
n
i
tor
Horizontal
Sync
Verticaf Sync
Composite Sync
Composite Blanking
Cursor Coincidence
!
Binary Addressing
of Video Memory
LJ
Row-Tabfe
Driven or Sequential Video Addressing
Modes
E
lrogrammable
Status
Row Position and
Address
Frgisters
!
Bidiiectional
Partial or
Fuf
l Page Smooth Scroll
I
Attribute Assemble
Mode
!
Double Height
Data Row"Mode
D
Double Width
Data
Row
Mode
!
Programmable DMA Burst
Mode
U
Configurable with
a
Variety of
Mem ory Contention
Arranqements
D
t-ignt
Fen Register
U
Cursor Horizontal
and
Vertical Position
Registers
D
Maskable
Processor Interrupt
Line
I
f
nternaf Status
Registe
r
I
Three-state Video Memory Address
Bus
n
Partial
or
Full Page Blank
Capabif
ity
E
Two Interlace Modes:
Enhanced
video
and
Alternate
Scan
Line
CRT Video Processor and
Controller
VPAC'
GENERAL DESCRIPTION
!
Ability
to Delay cursor and Blanking with
respect to
Active
Video
!
Programmable for Horizontal
Spf
it Screen
Applications
U
Graphics Compatible
! Ability
to Externally
Sync
each
Raster Line, each Field
U
Single
*5
Volt Power Supply
LJ
TTL Compatible
on
All
Inputs and Outputs
f
VT-100 Compatible
I
RS-170 lnterlaced Composite
Sync Available
PIN CONFIGURATION
VA2
1
VA1O 2
VA3
3
VA11
4
VA12
5
VA4
6
VA13
7
VAs
B
VA6
9
VA7
1O
VLT
11
lrS rz
FTS
Ig
Cffirq
DHE
Is
VD7 16
VD6
17
VD5
18
VD4
19
VD3 20
40 GND
39 VAg
38
VA1
37 VA8
36
VAO
35 CBLANK
34 CURS
sg
ncrc/f5C
gZ
CSYIIC/LPSTB
31 SLDiSLO
30
SfG'sLr
29 WBEN,USL2'CSYIIC
28 DMAR,SL3,VBLANK
27 INT
26
H-ST
256
24
VDO
23
VD1
22VDz
21
+ 5V
T
The CRT
9007
VPAC
"
is
a
next generation video
processor/
controlfer-an
MOS
LSI integrated circuit which supports either
sequentiaf or row-tabfe driven memory addressing modes.
As
indicated
by
the features
above, the
VPAC'"
provides
the user
with
a
wide fangg
of programmable features permitting low cost
impfementation of high performance CRT systems.
fts 14
address
lines
can direclly
address gF to
16K of video
memory. This
is
equivalent to eight pages of an 80 character
by 24line
CRT
dis-
pl.ay. Sm.oqth
gr
jump
scroff
operations may be performed
any-
where within the addressable memory.
In addition, status
rows
can be
defined
anyrvhere on the screen.
In
the sequentiaf video addressing mode,
a
Table Start
Register
points to the address of the first character of
the first data
rdw on
the
screen.
lt
can be easify changed to produce
a
scrolling effect
on the screen.
By using this register
in conjunction with two
aux-
ifiary address
registers and two Sequential
br-eak
registers,
a
screen
roll can be
produced with
a
stable status
row hefd
at
eitner the first
or last data row position.
fn
the
row-tabfe driven video
addressing mode, each row in the
video dispfay
is designated by its own address. This provides the
user
with greater flexibility than
sequential addressing since the
rows of characters are linked
by _pointers instead
of
iesiding
in
sequential memory locations.-Operations
such as data iow
insertion, deletion, and replication are easily accomplished
by
manipufating pointers instead of entire lines. The row table itself
can
be
stored
in
memory
in a linked list or in
a
contiguous format.
The VPAC'" works with
a
variety of memory contention schemes
incfuding operation
with
a
Single Row Buffer such
as the CRT 9006,
a Double Row Buffer such
as
the CRT
9212,
or
no
butfer at
all,
in
which case character addresses are output during each display-
able scan
line.
User accessable internaf registers provide such features as light
pen, interrupt enabling, cursor
addressing, and
VPAC'"
status.
Ten of these registers
are
used
for
screen formatting with
the abi-
lity to define over 200 characters per
data row and
up to
256 data
rows per frame. These
10 registers contain
the "vital
screen
parameters".
251