Tandy 2000 Service Manual page 637

82724
PREL[Nfl[NARV
During the Command Phase
of
the
Seek
operation the
FDC
is in the
FDC BUSY
state, but during
the
Execution
Phase
it
is
in
the
NON BUSY state.
While the
FDG
is
in
the
NON
BUSY
state, another Seek Command may
be
issued, and in this
manner parallef
seek
operations may
be done
on
up
to 4 Drives at
once.
ff
an FDD
is in a
NOT READY
state at the beginning
of
the command
execution phase or during the
seek opera-
tion, then the
NR (NOT
READY)
flag is set in
Status
Register
0
to a
1
(high), and
the command is terminated.
Note
that
the 8272A Read and
Write Commands do
not
have implied Seeks.
Any
R/W
command should
be
preceded by: 1) Seek
Command; 2) Sense
Interrupt
Status; and 3) Read
lD.
RECALIBRATE
This
command causes
the read/write head within
the
FDD
to
retract
to
the Track
0 position. The
FDC clears
the
contents of the
PCN
counter, and checks the status
of
the Track
0
signal
f
rom the
FDD.
As long as the Track
0
signal is low, the Direction signal remains
1
(high) and
Step Pulses are issued.
When the
Track
0 signal goes
high, the SE (SEEK END)
f
lag in Status Register 0 is set
to
a
1
(high) and the command is terminated.
lf
the Track
0
signal
is still
low
af te
r
77 Step Pulses have
been
issued, the
FDC
sets
the
SE
(SEEK
END)
and
EC
(EQUIP-
MENT CHECK)
f
lags
of
Status Register
0 to
both
1s
(highs), and terminates the
command.
The ability
to
overlap
RECALIBRATE
Commands to
multiple
FDDs, and
the loss of the
READY
signal,
ds
described
in the
SEEK Command,
also applies
to
the
RECALIBRATE Command.
SENSE INTERRUPT STATUS
An
Interrupt signal
is generated by the
FDC
for
one of
the following
reasons:
1.
Upon entering the Result
Phase
of
:
a.
Read
Data
Command
b.
Read a
Track
Command
c.
Read
lD
Command
d.
Read Deleted Data Command
e. Write
Data Command
f
.
Format a Cylinder Command
g.
Write Deleted Data
Command
h.
Scan Commands
2.
Ready Line
of
FDD
changes state
3.
End
of
Seek
or
Recalibrate Command
4.
During Execution
Phase
in the
NON-DMA Mode
Interrupts
caused
by
reasons
1
and
4
above occur during
normal command operations and are easily discernible
by the
processor. However, interrupts caused
by
reasons 2 and 3 above may be uniquefy
identified
with
the aid
of
the Sense Interrupt Status
Command. This
command when issued resets the interrupt signal
and
via bits
5,6,
and
7 of
Status
Register
0 identifies
the
cause
of the
interrupt.
Neither the
Seek
or Recalibrate Command
have
a
Result
Phase.
Therefore,
it
is mandatory to
use the Sense Inter-
rupt Status
Command
after these
commands
to
effec-
tively terminate them and
to
provide
verif
ication of
the
head
position
(PCN).
Table 11. Seek, lnterrupt Codes
SPECIFY
The
Specify Command sets the initial values for
each of
the three internal timers. The
HUT
(Head Unload
Time)
defines the time from the
end
of the Execution
Phase of
one
of the
ReadANrite Commands
to the
head
unload
state. This timer is programmable
f
rom
16
to
24A
ms
in
increments
of
16 ms
(01
=
16
ms,02=
32 ms
.
.
.
.
OF-
240
ms).The
SRT
(Step
Rate Time)
defines the time
in-
terval
between
adjacent step pulses. This timer is
pro-
grammable from
1
to
16
ms in increments
of
1 ms
(F=
1
ffis,
E=2
ffis,
D=
3
ms,
etc.).
The HLT (Head Load Time)
def
ines the time between when the
Head Load signal
goes high and
when
the
Read/Write operation
starts.
This timer
is
programmable
from
2
to
254
ms in
in-
crements
of 2
ms
(01-
2 ffis,
02=4
ffis,
03=6
ms,...
FE
=
254
ms).
The step rate should
be programmed 1 mS longer than
the minimum time required
by
the
drive.
The
time intervals mentioned
above are
a
direct
f
unction
of the clock (CLK
on pin
19).Times
indicated
above
are
for
an 8 MHz
clock,
if
the clock was
reduced
to
4
MHz
(mini-floppy application) then all time
intervafs
are
in-
creased by a
factor of
2.
The
choice of
DMA
or
NON-DMA
operation
is
made
by
the
ND
(NON-DMA) bit. When this bit is high
(ND-
1)the
NON-DMA mode is selected, and when
ND
-
0
the
DMA
mode
is
selected.
SENSE DRIVE STATUS
This command may be used
by
the
processor whenever
it
wishes
to
obtain
the
status
of
the
FDDs.
Status
Register 3 contains the Drive Status
inf
orrnation.
INVALID
lf
an invalid command is sent to the
FDC
(a command
not
def
ined above),
then the FDC
will
terminate the com-
mand. No interrupt is generated
by
the 82724
during
this
condition. Bit 6
and
bit 7 (DlO
and
ROM)
in the
Main
Status Register are both high
("
1") indicating
to
the
processor
that the
8272A
as
in the Result
Phase
and the
contents
of
Status Register
0 (ST0)
must
be read. When
the processor
reads
Status Register 0
it will find
an
BOH
indicating an invalid command was
received.
A
Sense Interrupt Status Command must be sent
af
ter
a
Seek
or
Recalibrate interrupt, otherwise
the
FDC
will
consider the next command
to
be
an Invalid
Command.
In some
applications
the user may
wish to
use
this
com-
mand as a No-Op
command, to
place
the FDC in
a
stand-
by
or
no
operation
state.
SEEK END
BIT
5
INTERRUPT CODE
CAUSE
BIT
6
BIT
7
0
1
'l
Ready Line changed
state, either
polarity
1
0
0
Normal Termination
of
Seek
or
Recalibrate
Command
1 1
0
Abnormal
Termination
of
Seek or Recalibrate
Command
6-234
AFN.O1259C