Tandy 2000 Service Manual page 562

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8259
A-8
TNTERRUPT
REQUEST REGTSTER (rRR) AND
|N-SERV|CE REGISTER (lSR)
The interrupts
at the
lR Input lines are handled by two
registers
in
cascade,
the
Interrupt Request
Register
(lRR) and the In-Service Register (lSR). The
IRR
is
used
to
store all the
interrupt
levels which are requesting
ser-
vice; and the
ISR
is
used to store
all the interrupt
levels
which
are being serviced.
PRIORIW
RESOLVER
This
logic
block determines the
priorities of
the bits
set
in the
lRR.
The
highest priority is
selected and strobed
into
the corresponding
bit of the
ISR
during [N-iT
pulse.
IIIITERRUPT
TASK REGISTER (IMR)
The IMR stores the bits which mask
the interrupt
lines
to
be masked.
The
IMR
operates on
the
lRR. Masking of
a higher priority input
will
not affect the
interrupt
roquest
lines
of lower priority.
rNT (TNTERRUPT)
This
output
goes
directly to
the CPU
interrupt
input. The
Von level on
this line
is designed
to
be
fully
compatible
with
the 8080A, 8085A
and
8086
input
levels.
|NTA
(TNTERRUPT ACKNOWLEDGE)
INTA
pulses will
cause
the
8259A
to
release vectoring
information onto the data bus. The
format of this
data
depends on
the system mode
(pPM)
of
the
8259A.
DATA BUS BUFFER
This
3-state,
bidirectional 8-bit
buffer is
used
to
inter-
face the
8259A
to
the system Data Bus. Control words
and status
information
are
transferred through the
Data
Bus Buffer.
READMRITE COI{TROL LOGIC
The
function
of this
block is
to
accept
OUTput com-
mands from the
CPU.
lt
contains
the
Initialization
Com-
mand Word (lCW) registers
and Operation
Command
Word
(OCW)
registers which store the various
control
formats for device operation. This function block
also
allows the status of
the 8259A
to
be
transferred onto the
Data
Bus.
eS (cHtP
sELEcr)
A
LOW
on this input
enables
the
8259A.
No reading or
writing
of the chip will occur
unless
the
device
is
selected.
wR (wRtTE)
A
LOW on
this input
enables
the
CPU
to write
control
words (lCWs and
OCWs)
to
the
8259A.
no
tneADl
A
LOW
on this input
enables the
8259A
to
send the
stetus of the
Interrupt
Rcquest Register (lRR),
f
n Service
Register (lSR), the Interrupt Mask Register (lMR),
or the
lntcrrupt
lcvcf onto thc
Data Bus.
Figure 4a.
8259A
Block Diagram
Figure 4b.
8259A
Block Diagram
As
This
input
signal is used in
conjunction with WT and
RT
signals
to
write
commands
into
the various command
registers,
as
well as
reading the various status registers
of the
chip. This
line can be
tied directly to
one
of the
ad-
dress lines.
ab
m
Ao
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AFN-OO221E