Tandy 2000 Service Manual page 533

intel
IAPX
186
INT3 CONTROL REGISTER
INT2 CONTROL REGISTER
-lll1Y
INTO
CONTROL REGISTER
DMA 1
CONTROL REGISTER
DMA
O
CONTROL REGISTER
TIMER CONTROL REGISTER
INTERRUPT
STATUS
REGISTER
INTERRUPT REQUEST REGISTER
IN-SERVICE REGISTER
PRIORITY MASK REGISTER
MASK REGISTER
POLL
STATUS
REGISTER
POLL
REGISTER
EOI
REGISTER
OFFSET
3EH
3CH
3AH
38H
36H
34H
32H
30H
2EH
2CH
2AH
28H
26H
24H
Figure 23. Interrupt Controller Registers
(Non-iRMX 86 Mode)
Priority Mask Register
This register
is
used
to
mask
all interrupts
below
particular interrupt priority
levels.
The format of this
register is
shown in Figure
25.
The code in
the lower
th
ree bits
of this
register inhibits interrupts
of
priority lower (a higher prrority
number) than
the
code
specif
ied. For example, 100
written into
this
register masks
interrupts of level
f
lve (101),
six (110),
and seven (111)"
The register is
reset
to
seven
(111)
upon
RESET
so all interrupts are
unmasked.
lnterrupt Status Register
This register contains general interrupt controller
status
lnf
ormation. The
f
ormat
of this
reg
ister
is
shown
in
Figure
26.
The bits in the status register
have
the following functtons:
DHLT:
DMA Halt Transfer; setting this
bit
halts
all
DMA
transfers.
lt
is
automatically
set
whenever
a
non-maskable interrupt
occurS,
and
it
is reset when an IRET instruction
is
executed.
The purpose of this bit
is
to
allow
prompt service
of all
non-maskable
inter-
rupts. This bit
may
also be
set by
the cPU.
lRTx:
These
th
ree bits represent
the
ind
ividual
timer interrupt request bits. These bits
are
used
to
differentiate
the timer
interrupts,
since the timer lR
bit in the interrupt
re-
quest register is the
"oR"
f
unction
of
all
tlmer interrupt
requests. Note
that
setting
any one
of these
three bits initiates
an inter-
rupt request to the interrupt controller.
Figure
24.
In-Service, Interrupt Request, and Mask Register Formats
Figu
re 25, Priority Mask Register Format
Figu
re 26.
Interrupt Status Register Format
30
AFN-02217C