Tandy 2000 Service Manual page 560

iru'
8259A/g25gA -Ag25gA-g
Tabfe
1.
Pin Description
Symbol Pln
No.
TyPe Neme end
Functlon
Vcc
28
I
Supply:
+5V
Supply.
GND
14
I
Ground.
CS
1
I
Chlp
Scloct:
A
low on this
pin
enables
RD
and
WR
communication
between the
CPU and th€
0259A.
INTA
functions
are independent ot
CS.
wn
2
o Wrllc:
A
low
on
this pin when
CS is low enables the
8259A to accept command words from the
CPU.
ND
3
I
Road:
A
low on this pin when
CS is low enables the
8259A to release status onto
the data
bus
for the
CPU.
h-Do
4-1
1
r/o
Bldlrcctlonrl
Date
Bur:
Control,
status and
interrupt-vector information
is
transferred
via
this
bus.
CAS9-CASz 12,13,
15
VO
Crtclda Llna.:
The
CAS
lines form
a
private
8259A bus
to control
a
multiple
8259A
structure.
These
pins are outputs lor
a master 8259A and inputs tor
a slave 8259A.
SP/EN
16
r/o Shve Progrlm/Eneble Bulfer:
This
is a
dual function pin. When
in the Buffered
Mode
it
can
be
used
as an
output
to
control bufler lransceivers
(EN).
When not in the buffered
mode it is used
as
an
input
to
designate a master (SP =
1)
or slave (SP
= 0).
INT
17
o Intcrtupt:
Thispingoeshighwheneveravalidinterruptrequestisasserted.ltisusedlointerruptthe
CPU,
thus
it
is connected to
the CPU's interrupt
pin.
I
Rs-l
R7
1
8-25
I
Intorlupt Rcquctta:
Asynchronous inputs. An
interrupt request
is executed
by
raising
an lB input
(low
to high), and holding it high until
it is acknowtedged (Edge
Triggered
Mode), or
just
by a high
level on an lB input
(Level Triggered
Mode).
INTA
26
InlaruPt
Acknowledgo:
This
pin
is used to enable
8259A
interrupt-vector
data onto the data bus
bv
a
sequence of interrupt
acknowledge pulses issued
by
the
CpU.
Ao 27
I
AO
Adclrc.. Unc:
This pin acts in
conjunclion with
the
CS, WR,
and
RD
pins. lt
is used
by the 8259A
to decipher
various Command Words the
CPU writes and status the
CPU wishes to read. lt
is
typically
connected to
the
CPU A0
addr€ss line (A1 for
iAPX
86, 88).
2-121
AFN.OO22l
E