Tandy 2000 Service Manual page 530

intel
|APX
186
Interrupt Controller Modes of Operation
The
basic modes of operation of the interrupt
con-
troller in
master mode are similar to the
82sgA.
The interrupt controller responds identically to
inter-
nal interrupts in all three modes: the difference
is
only in
the interpretation of function
of the
four exter-
nal
interrupt pins. The interrupt controller
is set into
one
of
these three modes by programming the
cor-
rect bits in the
f
NTO
and
lNTl
control registers.
The
modes
of
interrupt controller operation are
as
f
ollows:
Fully
Nested Mode
When in the
fully nested mode four pins are
used
as
direct interrupt requests. The vectors for these four
inputs are generated internally. An in-service bit
is
provided for every interrupt source. lf
a
lower-priority
device requests an interrupt while the in-service bit
(lS) is set, no interrupt
will
be
generated by the inter-
rupt controller. fn addition,
if
another interrupt
re-
quest occurs from the same interrupt source while
the inservice
bit
is set,
no
interrupt will
be generated
by
the interrupt controller. This allows interrupt
ser-
vice
routines to operate with interrupts enabled with-
out
being themselves interrupted by lower-priority
interrupts. Since interrupts are enabled,
higher-
priority interrupts will
be serviced.
When a
service routine is completed, the proper
lS
bit must
be reset by
writing the proper pattern to
the
EOI
reg
ister.
This
is
req
u
ired
to
allow
su
bseq
uent
interrupts from
this interrupt
source and
to
allow
servicing
of
lower-priority interrupts. An EOI
com-
mand is issued at the end
of the service routine just
before
the
issuance
of the return from interrupt
in-
struction.
lf
the fully nested structure has
been
upheld, the next highest-priority source with its
lS bit
set is
then
serviced.
Cascade Mode
The 80186 has
four interrupt pins
and
two of
them
have dual
f
unctions.
In
the
f
ully nested mode the four
pins are used as
direct interrupt inputs and the
cor-
responding vectors are generated internally. In
the
cascade mode, the four pins
are
conf
igured into
in-
terrupt
input-dedicated acknowledge signal
pairs.
The interconnection
is
shown in Figure 22.lNT0
is an
interrupt input intertaced
to
an
8259A, while
lNT2/lNTAO
serves as the dedicated interrupt
ac-
knowledge signal to that peripheral. The same
is
true
for lNTl and
11r113,r11115 .
Each
pair can selectively
be
placed in
the cascade or non-cascade mode by
pro-
gramming the proper value into
lNTO
and
lNTl
con-
trol
registers. The use of the dedicated acknowledge
signals eliminates the need
for the
use
of
external
logic to generate
lN-TA
and device select signals.
The primary cascade mode allows the capability
to
serve up
to
128
external interrupt sources through
the
use
of
external master and
slave 8259As. Three
levels
of priority are
created, r€quiring priority
resolution in the
80186
interrupt controller, the
mas-
ter 8259As, and the
slave
8259As.
lf an external inter-
rupt is serviced, one lS bit is set at each of
these
levels. When
the interrupt
service routine
is
com-
pleted, up to three end-of-interrupt commands
must
be issued by the programmer.
TIMER TIMER TIMER
DMA
DMA
0 1 2 0 1 |NTO
lNTl lNT2
lN
T3
N
Ml
TIMER
CONTROL REG.
INTERRUPT
PRIORITY
RESOLVER
INTERRUPT
REOUEST REG.
INTERRUPT
MASK
REG.
DMA
1
CONTROL REG.
EXT.
INPUT
O
CONTROL
REG-
PRIOR.
LEV.
MASK REG.
INTERRUPT
REQUEST TO
PROCESSOR
EXT.
INPUT
1
CONTROL
REG.
INTERRUPT
STATUS REG.
VECTOR
GENERA.
TION
LOGIC
INTERNAL ADDRESSIDATA
BUS
Figure 21. Interrupt Controller Block Diagram
27
AFN.02217C