Tandy 2000 Service Manual page 526

iru
|APX
186
DMA Acknowledge
No explicit DMA acknowledge pulse
is
provided.
Since both source and destination pointers
are
maintained, a read from a
requesting source, or
a
write to a requesting destination, should be
used
as
the DMA acknowledge signal. Since the chip-select
lines can be programmed to
be active
for a
given
block of memory or
lO
space,
and the DMA pointers
can be
programmed to point to the same given block,
a chip-select line
cou
ld be
used
to
ind
icate a
DMA
ac kn ow
I
ed ge.
DMA Priority
The DMA channels may be programmed such that
one
channel
is
always given
priority
over the other, or
they may be programmed such
as
to alternate cycles
when both have DMA requests pending. DMA cycles
always have priority over internal CPU cycles except
between locked memory accesses or word accesses
the odd memory locations: however, an external bus
hold takes priority over an internal DMA cycle.
Be-
cause
an
interru
pt
req
uest
can
not
suspend
a
DMA
operation and the
CPU
cannot access memory
dur-
ing
a
DMA cycle, interrupt latency time
will
suffer
during sequences
of
continuous DMA cycles.
An
NMI request, however, will
cause
all internal
DMA
activity to halt. This allows the
CPU
to
q
u
ickly
respond
to the
NMI request.
DMA Programming
DMA cycles will occur whenever the ST/STOP bit of
the Control Register is set. lf synchronized transfers
are
prog
ram
med,
a
DRQ
m
ust also
have
been
generated. Therefore,
the source and
destination
transfer pointers, and the transfer count register
(if
used) must be programmed before this
bit
is
set.
Each
DMA register may be modif ied while the chan-
nel is operating.
lf
the
CHG/NOCHG
bit is
cleared
when the control register
is
written, the
ST/STOP bit
of the control
register
will not be
modified by
the
write.
lf
mu
ltiple channel registers are
modif
ied, it
is
recom
mended
that
a
LOCKED
string
transf
er
be
used
to
prevent a DMA transfer
f
rom occurring
be-
tween updates to the channel registers.
DMA Channels and
Reset
Upon
RESET,
the
DMA channels
will
perform
the
f
ollowing actions:
.
The Start/Stop bit for each channel will be reset to
STOP
o
Any transfer in progress is aborted.
TIMERS
The
B01BO
provides
three internal 16-bit programma-
ble timers (see Figure
19). Two
of
these are highly
f
f
exible and are connected to
fou
r
external pins
(2
per timer). They can be used to
cou
nt
external
events, time external events, generate nonrepetitive
waveforms, etc. The third timer is not
connected to
any external pins, and is useful for
real-time coding
and time delay applications. In addition, this third
timer can
be used
as
a
prescafer to the other two, or
as a DMA request source.
DMA
REQ.
T2
INT.
REQ,
T2
OUT
TIMER
O
TIMER
1
TIMER
2
MAX COUNT
VALUE
A
MAX COUNT
VALUE
A
MAX COUNT
VALUE
B
MAX COUNT
VALUE
B
MAX COUNT VALUE
INTERNAL
ADORESSIDATA BUS
ALL 16 BIT REGISTERS
Figure 19. Timer Block Diagram
23
AFN-02217C