Tandy 2000 Service Manual page 525

intel
IAPX 186
TDRQ
O:
Disable DMA requests
from timer
2.
Enable
DMA requests
f
rom
timer
2.
Bit
3
Bit 3 is not
used.
f
f both
INC
and DEC are
specif
ied
for the
same
pointer,
the pointer will remain
Constant
after
each
cyc
I
e.
DMA Destination and Source Pointer
Registers
Each DMA
channel maintains a 20-bit source and
a
20-bit destination pointer. Each
of
these
poanters
takes up two
full 16-bit registers in
the
peripheral
control block. The lower four bits of the upper regis-
ter contain the upper four bits of the 20-bit
physical
address (see Figure 18a). These pointers may
be
ind
ividually incremented
or decremented
af
ter
each
transfer.
lf word transfers are performed the pointer
ls
incremented or decremented by
two. Each
pointer
may
point into either
memory
or
llO space.
Since the
DMA
channels can perform transfers
to or
f
rom odd
add
reSSeS,
there is no restriction on values
f
or
the
pointer registers. Higher transfer rates can be
ob-
talned
if all word transfers are performed
to
even
addresses, since this
willallow
data
to
be
accessed in
a
single memory
access.
DMA
Transfer Count Register
Each DMA channel maintains
a
16-bit transfer
count
register
(TC).
This register
is
decremented
after every DMA cycle, regardless of the state
of
the TC
bit
in
the
DMA
Control Register. lf the
TC
bit
in the DMA
control word is set or
unsynchronized
transfers are programmed, however, DMA activity
will
terminate when
the transfer count
register
reac
hes
zero.
DMA Requests
Data
transfers may be either source or destination
synch ron
ized,
that
is
either the
sou
rce
of the
data or
the
destination
of
the data may
request
the
data
transfer.
In addition, DMA transfers may be
un-
synch ron ized
; that is, the transfer
will
take
place
continually
until the correct number of transfers has
oCCurred.
When Source
or unsynchronized transfers
are performed, the
DMA channel may
begin another
transfer immediately after the end
of
a
previous
DMA
transfer. This allows
a
complete transfer to
take place
eve
ry 2
bus cycles
or
elght clock cycles (assuming no
wait states). No
prefetching occurs when destination
synchronization is
performed,
however. Data
will
not
be
fetched
f
rom
the source address until the destina-
tion
device
signals
that it
is ready
to receive it. When
destination synchronized transfers are
requested,
the
DMA
controller will relinquish contrbl of the
bus
after every transfer.
lf
no other bus activity is
in-
itiated,
another DMA cycle will begin after two
pro-
cessor clocks.
This is done
to
allow
the destinatton
device
time
to
remove
its request if another transfer
is not desired.
Sance
the
DMA
controller
will
relin-
quish the
bus,
the
CPU
can
initiate
a bus cycle. As
a
resu
lt, a
com
plete bus cycle
will often
be inserted
between
destination Synchronized transfers.
These
lead
to the maximum
DMA
transfer rates shown
in
Table
14.
Table 14. Maximum
DMA
Transfer
Rates
-t
Type of
Sync
h
ro
n
izatio
n
Selected CPU
1:
1
Unsynchronized
Source Synch
Destination Synch
Figure 18a. DMA Memory Pointer Register Format
Running
CPU
Halted
2
M
Bytes
sec
2
M
Bytes
sec
2MBytes
sec
2MBytes sec
l.3MBytes
sec
l.5MBYtes
sec
HIGHER
REGISTER
ADDRESS
LOWER
REGISTER
ADDRESS
15
XXX
DON'T CARE
xxx
XXX
XXX
A19-A16
A15-A12 A1
1-A8 A7-A.4
A3-AO
22 AFN.O2217C