Mitsubishi Electric QJ71LP21 Reference Manual page 271

8 TROUBLESHOOTING
Error Code
Error Contents and Cause
*1
(SD0)
• The high speed interrupt is set in a Q02CPU.
• The high speed interrupt is set in a multiple CPU
system.
3006 • The high speed interrupt is set when a QA1S
QA B is used.
• No module is installed at the I/O address designated by
the high speed interrupt.
The parameter file in the drive specified as valid
3007 parameter drive by the DIP switches is inapplicable for the
CPU module.
In a multiple CPU system, the modules for AnS, A, Q2AS
3009
and QnA have been set to multiple control CPUs.
The parameter-set number of CPU modules differs from
3010
the actual number in a multiple CPU system.
Multiple CPU setting or control CPU setting differs from
3012
that of the reference CPU in a multiple CPU system.
Multiple CPU automatic refresh setting is any of the
followings in a multiple CPU system.
• When a bit device is specified as a refresh device, a
number other than a multiple of 16 is specified for the
refresh-starting device.
• The device specified is other than the one that may be
specified.
3013
• The number of send points is an odd number.
In a multiple CPU system, the multiple CPU automatic
refresh setting is any of the following.
• The total number of transmission points is greater than
the maximum number of refresh points.
• In a multiple CPU system, the online module change
parameter (multiple CPU system parameter) settings
differ from those of the reference CPU.
3014
• In a multiple CPU system, the online module change
setting is enabled although the CPU module mounted
does not support online module change.
*1 : Characters in parentheses ( ) indicate the special register numbers where individual information is being stored.
*12 : This applies to the CPU of function version B or later.
*15 : This applies to the CPU with the serial No. of which first 5 digits "04102" or later.
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Corrective Action
• Delete the setting of the Q02CPU' s high speed
interrupt. To use high speed interrupts, change the CPU
module to one of the Q02H/Q06H/Q12H/Q25HCPU.
• To use a multiple CPU system, delete the setting of the
high-speed interrupt. To use high speed interrupts,
change the system to a single CPU system.
B or
• To use either the QA1S
setting of the high speed interrupt. To use high speed
interrupts, do not use the QA1S
• Re-examine the I/O address designated by the high
speed interrupt setting.
Create parameters using GX Developer, and write them
to the drive specified as valid parameter drive by the DIP
switches.
Re-set the parameter I/O assignment to control them
under one CPU module. (Change the parameters of all
CPUs in the multiple CPU system.)
Match the number of (CPU modules in multiple CPU
setting) - (CPUs set as empty in I/O assignment) with that
of actually mounted CPU modules.
Match the multiple CPU setting or control CPU setting in
the PLC parameter with that of the reference CPU (CPU
No.1).
Check the following in the multiple CPU automatic refresh
parameters and make correction.
• When specifying the bit device, specify a multiple of 16
for the refresh starting device.
• Specify the device that may be specified for the refresh
device.
• Set the number of send points to an even number.
Check if the following settings have been made in the
refresh setting of the multiple CPU setting, and correct the
settings as necessary.
• The total number of transmission points is within the
maximum number of refresh points.
• Match the online module change parameter with that of
the reference CPU.
• If the CPU module that does not support online module
change is mounted, replace it with the CPU module that
supports online module change.
Corresponding CPU
B or QA B, delete the
B/QA B.
MELSEC-Q
*15
Qn(H)
QnPRH
*12
Qn(H)
*12
Qn(H)
QnPH
*12
Q00/Q01
*12
Qn(H)
*12
Qn(H)
QnPH
*12
Q00/Q01
QnPH
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