Omron CJ1G/H-CPU series Operation Manual page 87

CJ1 and CJ1-H CPU Unit Comparison
Item
Text Text string and table
string, data processing
table instruction execution
data, and
data shift
instruc-
tions
Stack insertions/dele-
tions/replacements
and stack counts with
table processing
instructions
Data con- PID with autotuning
trol
instruc-
tions
Subrou- Global subroutines
tine
instruc-
tions
Failure Error log storage for
diagnosis FAL
instruc-
tions
Error simulation with
FAL/FALS
Data com- AREA RANGE COM-
parison PARE (ZCP) and
instruc- DOUBLE RANGE
tions COMPARE (ZCPL)
Index reg- Program and real I/O
ister real memory address com-
I/O patibility with CVM1/
address CV-series PLCs
conver-
sion for
CVM1/CV
Condition Compatibility with
Flag sav- CVM1/CV-series
ing and PLCs
loading
54
CJ1-H CPU Unit
(CJ1H-CPU6@H)
Data processing can be
performed normally or in
the background (specified
for each instruction).
(Using time slices to pro-
cess instruction over sev-
eral cycles reduces the
effect of these instructions
on the cycle time.).
Supported.
Effective for tracking work-
pieces on conveyor lines.
Supported (eliminating the
need to adjust PID con-
stants).
Supported (GSBS, GSBN,
and GRET instructions)
Enables easier structuring
of subroutines.
Supported.
FAL can be executed with-
out placing an entry in the
error log. (Only system
FAL errors will be placed in
the error log.)
Supported.
Fatal and nonfatal errors
can be simulated in the
system to aid in debug-
ging.
Supported.
CVM1/CV-series real I/O
memory addresses can be
converted to CJ-series
addresses and placed in
index registers or CJ-
series real I/O memory
addresses in index regis-
ters can be converted to
CVM1/CV-series
addresses.
Condition Flag status can
be saved or loading using
the SAVE CONDITION
FLAGS (CCS) and LOAD
CONDITION FLAGS
(CCL) instructions,
enabling applications
where Condition Flag sta-
tus must be passed
between different program
locations, tasks, or cycles.
CJ1M CPU Unit
(CJ1M-CPU@2/CPU@3)
Data processing can be
performed normally or in
the background (specified
for each instruction).
(Using time slices to pro-
cess instruction over sev-
eral cycles reduces the
effect of these instructions
on the cycle time.).
Supported.
Effective for tracking work-
pieces on conveyor lines.
Supported (eliminating the
need to adjust PID con-
stants).
Supported (GSBS, GSBN,
and GRET instructions)
Enables easier structuring
of subroutines.
Supported.
FAL can be executed with-
out placing an entry in the
error log. (Only system
FAL errors will be placed in
the error log.)
Supported.
Fatal and nonfatal errors
can be simulated in the
system to aid in debug-
ging.
Supported.
CVM1/CV-series real I/O
memory addresses can be
converted to CJ-series
addresses and placed in
index registers or CJ-
series real I/O memory
addresses in index regis-
ters can be converted to
CVM1/CV-series
addresses.
Condition Flag status can
be saved or loading using
the SAVE CONDITION
FLAGS (CCS) and LOAD
CONDITION FLAGS
(CCL) instructions,
enabling applications
where Condition Flag sta-
tus must be passed
between different program
locations, tasks, or cycles.
Section 1-6
CJ1 CPU Unit
(CJ1G-CPU4@)
Normal processing only.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.