Battery-Free Operation With Flash Memory; Better Compatibility With Other Sysmac Plcs; Cj1M Cpu Unit Features - Omron CJ1G/H-CPU series Operation Manual

CJ1-H and CJ1M CPU Unit Features
Delayed Power OFF
Processing for Specified
Program Areas
1-3-4

Battery-free Operation with Flash Memory

1-3-5

Better Compatibility with Other SYSMAC PLCs

C200HE/HG/HX PLCs
CVM1/CV-series PLCs
1-3-6

CJ1M CPU Unit Features

Built-in I/O
General-purpose I/O
Interrupt Inputs
High-speed Counters
The DI and EI instructions can be used to disable interrupts during specific
portions of the program, for example, to prevent the power OFF interrupt from
being executed until a specific instruction has been executed.
Any user program or parameter area data transferred to the CPU Unit is auto-
matically backed up in flash memory in the CPU Unit to enable battery-free
operation without using a Memory Card.
Note Refer to information on flash memory in the CS/CJ Series Programming Man-
ual (W394) for precautions on this function.
The AREA RANGE COMPARE (ZCP) and DOUBLE AREA RANGE COM-
PARE (ZCPL) instructions are supported in the CJ1-H CPU Units to provide
better compatibility with the C200HE/HG/HX PLCs.
The CONVERT ADDRESS FROM CV instruction allows real I/O memory
addresses for the CVM1/CV-series PLCs to be converted to addresses for the
CJ-series PLCs, enabling programs with CVM1/CV-series addresses to be
quickly converted for use with a CJ-series CPU Unit.
The CJ1M CPU Units are high-speed, advanced, micro-sized PLCs equipped
with built-in I/O. The built-in I/O have the following features.
■ Immediate Refreshing
The CPU Unit's built-in inputs and outputs can be used as general-purpose
inputs and outputs. In particular, immediate I/O refreshing can be performed
on the I/O in the middle of a PLC cycle when a relevant instruction is exe-
cuted.
■ Stabilizing Input Filter Function
The input time constant for the CPU Unit's 10 built-in inputs can be set to 0 ms
(no filter), 0.5 ms, 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, or 32 ms. Chattering and
the effects of external noise can be reduced by increasing the input time con-
stant.
■ High-speed Interrupt Input Processing
The CPU Unit's 4 built-in inputs can be used for high-speed processing as
regular interrupt inputs in direct mode or interrupt inputs in counter mode. An
interrupt task can be started at the interrupt input's rising or falling edge (up or
down differentiation.) In counter mode, the interrupt task can be started when
the input count reaches the set value (up-differentiated or down-differentiated
transitions.)
■ High-speed Counter Function
A rotary encoder can be connected to a built-in input to accept high-speed
counter inputs.
Section 1-3
15