Bus Transceivers; External Trigger Circuit; Signature Analysis (Sa) Test Modes - HP 3456A Operating And Service Manual

Service
8-289. The Main Controller Jl.P scans V9 via the AO-A2
address lines. Tri-State Buffer V I 6 is enabled during
these scan periods when the ASE (Address Switch
Enable) line at V9, pin 4 goes low. The address code set
by the AISI switches is read by the lAP (via the 8-bit data
bus) at this time. The position of switch contacts 1-5 is
used to set the HP-IB address for the 3456A. Switch 7 is
closed when the 3456A is to be used as a talk-only
device. Data lines DO-D5 are pulled high by the 10 K
pull-up resistors (R8-RI3). These lines are set low
(ground) when the associated address switches are clos­
ed.
8-290. Bus Transceivers A3V12,
U14. Each Bus Transceiver has four independent tri­
state driver/receiver pairs. The direction of the data
flow for each pair is controlled by its corresponding
send/receive input. The disabled output of the pair is
forced to a high impedance state. Pins 4 and 12 (the
Pull-Up Enable inputs) of each transceiver are tied to
ground which puts the drivers in
figuration. Figure 8-57 lists the SIR, Data. and Bus con­
nections for each transceiver pair and also gives a truth
table showing the direction of the Information Flow
based on the logic level applied to the SIR input.
8-291 . The Talker/Listener line (pin 27) from U9 drives
pins I , 7, 9, and 1 5 to V I 2 and U7 and pins 1 , 7, and 9
to U8. When this line is high, data flows from V9
through the transceiver to the bus. When U9 pin 27 is
low, the data flows into U9. The EOl line connected to
U8 is controlled by the T/Rl line from V9. Transceiver
VI4 is programmed (pins I , 7, and 9 to ground. Pin 1 5
+
to 5 V) so that information flow on the REN, ATN,
and IFC can only be from the bus to V9. The flow for
the SRQ line can only flow from V9 to the bus.

8-292. External Trigger Circuit.

Schematic 1 3 , HP-IB Logic). The External Trigger Cir­
cuit is not part of the HP-IB circuit but it does use the
same tri-state buffer used by the HP-IB circuit. The in­
put to this trigger circuit is via the External Trigger in­
put connector (141. BNC) located on the rear panel. The
+
input line is tied to 5 V via pull-up resistor R2. Series
resistor R3 and diodes CR3 and CR4 are used for input
protection.
8-293 . When a negative trigger pulse is applied to J41. it
is inverted by U4a and used to clock the high appearing
at the D input (pin 2) of U5a to the Q output (pin 5).
This high is fed to pin 1 6 of tri-state buffer A3UI6 and
strobed thorugh to the Main Controller Jl.P when the
ASE line (enable. pins I and 19) goes low. The ASE line
goes low when the Main Controller Jl.P scans U9 via its
AO-A2 address lines.
8-294. Refer to Paragraph 8-250(d) for a description of
the Voltmeter Complete output line.
8-52
U7, U8, and
an
open collector con­
(A3 Board, see
8-295. Signature Analysis (SA) Test Modes (A4 Board,
see Schematic 9, Main Controller).
troller has four jack/plug connections, each of which
can be changed for SA troubleshooting. The node
signatures obtained during the SA tests are used to iden·
tify faulty logic nodes for troubleshoOling to the com­
ponent level. A choice of different strobe connections is
available for the start/stop input to the SA test equip­
ment. Following is a brief description of each SA test
mode and the start/stop strobe points used for these
tests.
a. J9/P9-RUN/ROM SA. Plugs P9 and P 1 2 must
both be in their ROM SA position and the Data Bus
Break, E5. must be removed before ROM SA tests can
be made. The other plugs (PlO and P I I) must be in their
RUN positions. Plug P9 connects data line 05 and 07
to ground through diodes CRI and CR2. Data lines
00-04 and 06 are tied to + 5 V via the 100 K pull-up
resistors (R5). Plug PI2 breaks the VMA signal path
from UI8b to the UI7 and UI9 Line Decoders.
b. JJO/PJO-RUN/RAM SA . Plug P l O must be in
its SA position and P9, PI I , and PI2 in their RUN posi·
tion and E5 inserted in it socket before RAM signatures
can be taken. Plug PlO breaks the A3 address line path
to the U8 ROM and grounds the A3 line to U8 when it is
positioned in the RAM SA position.
Pin Connection.
p.ir
•• Input
Control
Dill
SIR
A 1
• 7
C 9
0
1 5
SIR .. Send/Receive
PUE Pull·Up Enable
=
Trut� T.ble
IRfo.
Dir.ttion
SIR PUE
Flow
Data - Bus
0 X
Data - Bus
0 Data - Bus
X Don't Care
=
Positive True Logic
Figure 8·57. QUid Bidirectional Transceiver IHp·IBI.
Pin Configuration .nd Truth Tabl, (HP·IB).
Model 3456A
The Main Con­
..
.
PUE
,
3 4
6 5
4
1 0 1 1 1 2
1 4 1 3 1 2
Comments
Active Pull·Up
Open Collector