Read Only Memory (Rom); Random Access Memory (Ram); Isolation Logic (A3 Board) - HP 3456A Operating And Service Manual

Service
Complete Connector (BNC) on
voltmeter. Input protection diodes are located on the A3
board for this line.
e. Isolation Logic Strobe (U19, pin
tion Logic control circuits (both transmitter and
receiver) are strobed when the �P wants to transfer data
via the Isolation data lines. The Read /WiTte Jine from
the Outguard Controller determines whether this strobe
is used to transmit or receive data.
I
RAM Select (U19, pin 15).
when the RAM's are addressed by the �P. The RAM
Select line and the Read/Write line are used with the
Chip Select (CS), Write Enable (WE), and Output
Enable (OE) circuits to control the RAM read·write
operations. SA
g. Strobes (UI7, pins 9 and ID).
lines are used for the Start and Stop inputs for the
signature analyzer during SA testing.
h. Annunciator Strobe (Un, pin 1J).
used with nip·flop A4U24b to generate a wider write
strobing pulse for the Annunciator driver (A4V30).
i. Display Strobe (U17, pin 12).
nip-flop A4V24a to generate a wider write strobing
pulse for the Display driver (A4V29).
j. Ke yboard Clear (Un, pin 13).
as a clear input to A4V22a and A4V22b to clear the
Keyboard Interrupt.
k. Ke yboard Strobe (Un, pin 14).
used as an output enable for both the Key Encoder
A4V21 and the Tri·State Buffer A4V2S. Encoded
keycode information is sent to the �P via the data bus
during this strobe period.
I. Hp·IB Select (Un, J! . in 15).
strobe line is the chip select (CS) for the HP-lB Interface
Adapter (A3V9).

8-151. Read Only Memory (ROM).

(firmware) used to control the measurement operations
64
are recorded into three ROM's (VS, V7, and V8). Each
ROM has K bits (8192 words of 8 bits each) of
memory. These devices have tri-state outputs that are
controlled by their CE (chip enable, pin
8-2S2. Refer to Paragraph 8-239 (Address Bus) and
Paragraph 8-247 (Peripheral Select Decoders) to see
how a ROM address location is selected. At access time
(CE), the data in the selected address location is read via
the 8-bit data bus into the �P.
8-2S3. The initial 34S6A production runs had six (VI,
U2, V4, VS, V7, and V8) 32 K bit ROM's (see
Schematic 9, Ma in controller). Since
are now being used, ROM's V I , V2, and V4 are not us·
ed. JMPRA, B, and C (located below A4V6 on
64
Schematic 6) were used to change from 32 K ROM
operation to K ROM operation.

8-154. Random Access Memory (RAM).

read/write IC devices (VlO and U I I) are used to store
8-48
the rear of the
measurement data. Each RAM has I K byte (I K x 8
bits) of memory. Only 1400 bytes of the 2 K RAM
/4).
memory is used for measurement data. The remaining
memory (2 K minus 14(0) is used as a scratchpad (in­
The l5Ola·
termediate data needed for final results. etc.). Four
bytes are required for each reading, therefore, the max­
imum number of readings is 3S0 (1400 +4).
8·2SS. Address bus lines AO·A9 are used to access the
RAM memory locations. The RAM's 8-bit I/O data bus
This line is strobed
lines are tri-state. A RAM is in the read mode whenever
its Write Enable line (WE·L, pin 21) is high. The Chip
Select line (CS-L, pin 18) and the Output Enable line
(OE-L, pin
of the output data. A RAM is in the Write mode
whenever the WE-L and CS-L control lines are low.
These strobe
8·256. Isolltion logic (A3 BOlrd,
This line is tion logic).
8-157. General.
transmitter which sends information to the Inguard and
This line is used with
a receiver which receives information from the Inguard .
Both use transformers for coupling. Each transformer
consists of windings on a toroidal core and a single wire
This strobe is used
passing through the center of the core for coupling .
Transformer coupling allows the Outguard ground
which is connected to earth ground to be isolated from
This strobe is
the Inguard ground which is connected to the low input
terminal.
8-158. TransmlUer.
(A4VIS) is transferred across the 8·bit data bus to
The Hp·IB Select A3UIO, a parallel to serial shift register. Data is loaded
into UIO when a high to low transition occurs on its
load/shift input (pin I). This transition is generated by
VISb when a high occurs on its clear input (pin 13); this
The programs sets the Q output of VISb (pin 9) low. Serial data shift
out of VIO occurs (at the clock rate) when the load/shift
input ...!2. .. .- VIO goes high.
Read/Write line (D input to UI Sb) goes low (inverted by
20)
V2a) followed by a low to high transition on the Isola­
tion Logic Strobe line (clock input to UISb).
input.
8·2S9. An extra bit (byte-available bit) is added to the
8·bit byte by VISa. Flip-flop UISa is always reset to one
so that this extra bit is always a "one". This is the last
bit in and will always be the first bit transmitted out.
The byte-availablejlit tells the Inguard �p that data is
ready. The Q and Q outputs of VISa are fed to parallel
connected gates to provide the required drive for TI's
64
primary. The 9-bit data group is gated through V 19 by
K bit ROM's the clock appearing at the output of V13a.
8·260. The I.S MHz Master Clock (Bus 4>2) is divided
by two in V l l b and the Q output of VJ J b (Bus 4>2+2) is
divided aga in by two in Vl7a (Bus 4>2+4). The pro­
pagation delay time of inverters V6b and c and V2b and
The RAM c is used to delay the Bus q:.2+2 clock at Vl3a, pin 2 to
compensate for the clock delay through Ul7a.
20)
(lines tied together) control the transfer
see
Schemltic 12, lsoll'
The Isolation Logic consists of a
Data from the
This occurs when
Model 34S6A
o
Outguard �P
the
o