Ale Clock For A/D Converter; Frac - HP 3456A Operating And Service Manual

can be monitored at TP3. The output from U I 2c and
UI2d provide the 2-phase crystal reference inputs for
U I 3. The output from the crystal reference is also fed
(via inverters U l 2 f and U 1 2e) to the circuits that
stabilize and clean up the ALE clock appearing at U6b,
pin 9-the ALE clock for the AID Converter.
8-199. ALE Clock for AID Converter.
used for slope generation in the AID Converter must
occur within a certain time frame and be free of jitter
and noise. Four D-type positivie edge-triggered nip­
naps (U6a, U6b, U7a, U7b), hex inverters U8a-d, and
NAND gates USa-d are con figured to meet these re­
quirements. Flip-naps U7a and U7b are preconditioned
by connecting their preset (pins 4 and 10) and D input
(pins 2 and 12) to + S V via a pull-up resistor. This
allows U7a and U7b to be reset by their own "Q" out­
puts (outputs delayed and inverted by U8 inverters). The
output of U7a is a pulse train (approximately 0 to + 3 .2
V, 40 ns pulse width) occurring at the crystal oscillator
o 60
frequency. U7b's output is a pulse train (approximately
+
to 3.6 V, ns pulse width) that occurs at the ALE
clock rate. Applying these pulse trains
USa, and USa's output to nip-nap U6a provides strobe
pulses for USb and USd. These strobes will change when
necessary to advance or delay slightly the clock pulses at
USc's output. The output of USe is used to strobe the
ALE clock pulses through U6b ensuring that the ALE
pulses occur during the desired lime period and are free
of jitter and noise.
8-200 Refer to Figure 8-44 (FRAC Circuits)
for the following circuit discussion. The FRAC (Five
Rundown ALE Counter) circuit is part of a large loop
that includes the A 13 .uP and the integrator/comparator
circuits in the AID Converter. The FRAC looks at both
the polarity bit (HSA) from U 13 and the comparator bit
(HCP) from the AID comparator during rundown. The
HSA and HCP logic levels contain slope information
which FRAC uses to start or stop the slope in Ihe in­
tegrator circuit. The FRAC counts the lime the slopes
are on by strobing the .uP's internal counter (U 13, pin
39) on every Sth ALE during rundown, if an S
S + 2, or S I slope i s on. Each time period between
-
these strobes is equal to one AID count, therefore S
ALE's equal one AID count (I2.82 microseconds for
Hz, IS.38 microseconds for SO Hz). The.uP counts these
AID time periods during rundown and computes the
measurement value.
8-201. F R AC's Function During Rundown.
8-42 (Slope Sequence During Rundown) illustrates the
slope sequence during rundown and the FRAC actions
that occur during rundown that control the slope
generation. Refer to the AID Converter theory section
(Paragraph 8-70) for additional information regarding
the AID Converter and Slope Generation.
The ALE clock
8-202. Four different slopes are used during rundown
to achieve highly accurate measurements of the residual
voltage remaining on the AID Converter's integrator
after runup. The first type of slope (called S ± 4) is the
steepest and it continues for an imeger number of AID
counts. After the slope has crossed zero, S
exactly a decade less in steepness, is applied. After S
crosses zero, S + 2 ( 1 / 100 S + 4 slope) is applied and
after this crosses zero, S - I (1/1000 5 + 4 slope) is ap­
plied. The time duration of each slope is counted se­
quentially, with that count subsequently being stored in
memory, to develop the least significam digits during
rundown.
10
8-203. FRAC will not slap counting at the exact instant
NAND gate
+
that zero-crossing occurs during the 5 ± 4, 5 - 3, and
S
2 slopes nor will these slopes slop immediately at
zero-crossing. The counting and slopes stop at the next
AID count after zero crossing (see T
therefore FRAC knows that zero-crossing has occurred
but does not know the exact time that is happened. This
delay accounts for the overshoots shown in Figure 8-42.
During the final rundown slope, the S
off shortly after zero-crossing-on an ALE count versus
an AID count.
8-204. The .uP always has an S + 0 period rcady
follow a slope period after zero-crossing occurs. FRAC
stops couming during a S + 0 period which allows time
ror the logic circuits to make circuit condition checks
and decisions.
8-20S. The same slope pattern will always be repeated
±
during rundown-this is controlled by the ROM pro­
4, S gram in U J 3. It is FRAC's responsibility during run·
- 3 ,
down to: ( I ) generate the AID counts and strobe U 1 3 at
60
each counl, (2) determine if the first 5 ± 4 slope is the
correct polarity, (3) determine when zero crossing oc­
curs, (4) stop counting at the next AID count after zero
crossing occurs, (S) start counting at the beginning of
each slope.
Figure
- 3 , which is
- 3
8,
Figure 8-42),
I slope is turned
�
10
8- 37