Keyboard Scan Logic; Keyboard Scan Circuits - HP 3456A Operating And Service Manual

Model 34S6A
8-261. Presettable counter, U I , is a 4-bit counter that is
configured as a count·to·nine circuit (uses only the QA
and QD outputs). At the count of nine, the QA and QD
outputs are high. These highs (through U3a and U6d)
causes the output of Ul3b to go low. This low is used as
as clear for U ISb, U l7a, and U I . The Q output of U ISb
goes low at this time putting a low on the J and K inputs
of Ul7a (this stops UI7's toggle counting). When UI7a
is cleared, its Q output goes high which disables gate
Ul3a. The clock path to UIO, UISa, UI9, and UI is
disabled until the next write command occurs.
Receiver. The serial data received from the In­
8-262.
guard Logic through transformer T2 consists of a group
of 9 bits with the first bit always a "one". The receiver
uses this first bit to generate Byte Available. Clock and
data are derived from the serial data by U21, a tran·
sistor array circuit . This clock is used to shift the data
into U22, a serial to parallel shift register, and is also
used by the Byte Available flip·flop U17b. The Q output
of Ul7b goes high on the clock pulse following the shif­
ting of bit " one" to pin 1 3 0f U22/pin 1 1 of U l 7b. This
high is used to tell the Outguard �P that a data byte is
available on the data bus. The first bit is then shifted out
of U22 (overflow) leaving the eight-bit data byte on the
parallel output of U22.
8-263. The Byte Available pulse from U l 7 b goes to
A3U16, pin 1 8 (data line 07. see Schematic 1 3 , HP·IS
Logic). The Byte Available pulse is transferred through
UI6 to the Outguard �P when the ASE enable line (pins
I and 1 9 ) goes low. An enable on the ASE line occurs
when the �P scans U9 via the AO·A2 address lines.
When the �P receives the Byte Available pulse, the
following sequential events take place: (I) the OBE
(Data Bus Enable) line goes high which clears flip-flop
U l la; (2) the Read line goes high and the Isolation
Logic Strobe line goes low. The Read signal (inverted by
U2a) and the Isolation Strobe pulse are applied to AND
gate U13a. The output of UlJa is used as an enabling
level for tri·state buffer U20, a clock for flip· flop U I la,
and a clear for flip· flop U 17b. The 8-bit byte is transfer·
red from buffer U20 to the I'P and the U22 shift register
is cleared at this time.
8·284. Keyboerd Scen logic tA4 BOlrd. HI Schemltic
10, Keybolrd Scen logic. DispllY Ind Annunciltor Drive;
AZ BOlrd . ... Schlmltic 1 1 . Keybolrd, displlY end An·
nunciltor).
Genenl. The main sections in the Keyboard
8-26S.
Scan Logic are a X-Y matrix (front panel switches), a
matrix encoder (A4U21 and U22b), a keyboard inter·
rupt circuit (A4U22a), and a tri·state data buffer
(A4U25). A keyboard interrupt signal is sent to the
Outguard I'P whenever a front panel key is pressed. The
I'P responds by strobing in the encoded keyboard infor·
mation.
8-266. Keyboard Scan Clrculls.
a basic 4xS switch matrix with a capacity for decoding
Figure 8-S3 illustrates
Figurl 8·53. 4 x 5 Switch Matrix (S18 Clolld).
20 switches (only one switch can be closed at a time).
Switch SI8 is closed in the illustration; this closure con·
nects the X2 and YS matrix lines. The 34S6A has 37
front panel switches (excluding the off-on lines switch)
so a 4xl0 matrix with a capacity of 40 is required (see
Figure 8-54).
8-267. The XI, X2, X3, and X4 matrix lines are tied to
the A4U21 Key Encoder (20 Key Encoder) pins 12, 1 1 , 9
and 8 respectively. The YI, Y2, Y3, Y4, and YS Hnes are
tied to U21 pins I , 2, 3, 4, and S respectively. The
Y 1 '-YS' lines are also tied to U21 pins I-S but their con­
nections are through resistor-diode isolation networks
(RI6-R27 and CR3-CR7, see Schematic 10). The
resistor-diode network (along with U26 and U22b) ex·
pands the 20·key encoder system to a 4O·key system.
The YI '-VS' lines are also connected to U22b via U26,
an 8-input OR gate (unused inputs tied to
flop U22b outputs a high to pin 14 of buffer U2S (goes
to data line 05) whenever a Y' key is pressed. This ar­
40
rangement provides the I'P with the n�essary decoding
D4
capability for a key encoder (high on data line
Y' key; low ::: Y key).
=
Figure 8·54. 4 x 1 0 Switch Mltrix On AZ BOlrd.
8-268. Pin 1 3 of Encoder U21 goes high whenever a
front panel switch is pressed. This output goes to buf­
fers U27b and U27a which provides the drive for the
clock inputs to U22a and U22b (U21 is CMOS with
limited drive capability). The Q output of U22a is set
low (Keyboard Interrupt) by a high on its clock input
due to the PR and 0 inputs being tied to + S V. A high
on the clock input of U22b will set its Q output high if a
high appears on its 0 input (high on 0 when Y' key has
been pressed). A low pulse on the Keyboard Clear line
resets U22a and b after the keyboard switch information
has been strobed into the I'P.
8-269. A low on the Keyboard Strobe line going to U21,
pin 14 and U2S, pins I and 1 9 dumps the contents of
U21 to U2S and then dumps U2S to the data bus where
the I'P reads the key codes. The pull-up resistor (RI4),
Service
.. !-o\I.
..
+
S V). Flip­
8-49