Outguard Section (A3 And A4 Boards); Main Controller Circuits (A4 Board); Simplified Block Diagram, - HP 3456A Operating And Service Manual

Model 3456A
8·224. Outguard Section (A3 and A4 Boards).
8·225. General.
8·226. The Outguard Section is divided into the follow­
ing groups for the theory of operation (see Figure 8-45,
Simplified Block Diagram, Outguard).
a. Main Controller Circuits(A4 Board)
I . Microprocessor . . . . . . . . . . . . . . . . . . . . 8·232
2.
Clock Generator . . . . . . . . . . . . . . . . . . . 8-236
3 . Address Bus . . . . . . . . . . . . . . . . . . . . . . . 8-239
4. Data Bus and Data Transfer . . . . . . . . . 8-240
5 . Peripheral Select Decoders . . . . . . . . . . 8·247
6. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 8-251
Isolation Logic Circuits (A3 Board) . . . . . . . 8·256
b.
1 . Transmitter . . . . . . . . . . . . . . . . . . . . . . . 8-258
2. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . 8-262
c. Keyboard Scan Logic (A4 Board) . . . . . . . . 8-264
1 . Keyboard Scan Circuits . . . . . . . . . . . . . 8-266
2.
Display Ready Circuit . . . . . . . . . . . . . . 8-271
d. Display and Annunciator Drive
(A4 Board) . . . . . . . . . . . . . . . . . . . . . . . . . 8·272
1. Control Circuits for Data
Transfer . . . . . . . . . . . . . . . . . . . . . . . . 8-274
2. Display and Annunciator Driver
Systems . . . . . . . . . . . . . . . . . . . . . . . . 8-277
3 . Sample Rate Indicator Circuit . . . . . . . . 8·279
e. Keyboard, Display, and Annunciator
Circuits (A2 Board) . . . . . . . . . . . . . . . . . . 8-280
f. HP-IB circuits (A3 Board) . . . . . . . . . . . . . . 8·285
I . HP-IB Interface Adapter . . . . . . . . . . . . 8·287
2. HP-IB Transceivers . . . . . . . . . . . . . . . . 8·290
g. External Trigger Circuit (A3 Board) . . . . . . 8·292
h.
Signature Analysis (SA) Test Modes . . . . . . 8-295
8·227. The 3456A is a microprocessor·based instrument
that uses software rather than hardware to perform
many of the instrument's functions. The software pro­
grams are stored in the Outguard ROM (Read Only
Memory).
8-228. The Main Controller in the Outguard Section
controls the measurement operations that are per­
formed by the Inguard
microprocessor (p.P) is a slave of the Outguard ItP. The
Outguard I'P uses the reset line going to the Inguard ItP
for a master synchronizing control in addition to sen­
ding the Inguard I'P measurement operation com­
mands. Communications between the Outguard and In­
guard Controllers is through the Isolation Logic (see
detailed block diagram on the foldout page preceeding
the schematics).
8-229. The Ma i n Controller also manages the com­
munications between the Front Panel Control/HP-IB
interface and performs the math calculations.
Paragraph
circuits. The Inguard
8-230. A memory mapped
used in the 3456A. The
Keyboard, Isolation Logic, and HP-I B) are treated as
memory addresses so that reading or writing can be
completed in one memory instruction. Address loca­
tions are decoded by 3 to 8 line decoders (A4V6, V17,
and U19) to generate strobes (see schematic 9, Main
Controller). These strobes enable the device/s addressed
by the I'P during a read or write routine.
8·231. Main Controller Circuits (A4 Board).
8-232. Microprocessor (A4U15).
Main Controller (Outguard)
MC68AOOP. The "A" in the device type signifies that
4> q,
its clock rate is 1 . 5 MHz rather than the standard I
MHz. The one and two pins (V15 pins 3 and 37
respectively) are inputs for the external two-phase, non­
+
overlapping clock that is generated by A4U14. These
clock signals are 0 V to
110
8-233. The Main Controller ItP communicates with
ROM, RAM, and the
an
bus and 8-bit data bus. The 16-bit address buS" pro­
vides the I'P with the capability of addressing up to 64K
locations. The 8-bit data bus is bidirectional as well as
tri-state.
8·234. The following control signals are used by the
Main Controller ItP:
a. IRQ ( pin 4)--lnterrupt Request. This input line
receives Keyboard Interrupt signals from A4V22a, pin
6. IRQ (logic low) requests that an interrupt sequence be
generated when keyboard information is ready to be
sent to the ItP.
b. VMA ( pin 5)·· Va/id Memory Address. When
high, VMA indicates to all peripheral select circuits that
the address bus contains valid information. VMA is
retimed (becomes True VMA) before it is used by the
peripheral select circuits. See Paragraph 8-245 for the
True VMA circuit and timing descriptions.
NMI ( pin 6)-- Nonmaskable Interrupt. This input
c.
line is connected to the Interrupt Request output line
from the HP-IB Interface Adapter (A3U9, pin 40). The
NMI line is set low when HP-IS data is available for
transfer to the ItP.
d. R/W ( pin 34)--Read/Write. This output line is
used for the RAM, HP-IB, and Isolation Logic circuits
to control their Read and Write operations. A high on
this line signals these circuits that the JlP is in a Read
state. A low signals a Write state. A Write Going To
Read Stretcher circuit increases the time period that the
Write is held true. See Paragraph 8-244 for the Stretcher
circuit and timing descriptions.
e. DBE ( pin 36)--Dara Bus Enable. This input signal
tells the ItP how long it is supposed to drive the data bus.
When OBE is high, it permits data to be output during a
write cycle. The data bus drives are disabled internally
during read cycles. A OBE Stretcher circuit holds the
data longer than the normal IOns. See Paragraph 8-242
for the Stretcher circuit and timing descriptions.
Service
110
110
address bus technique is
peripherals (Display,
The ItP used in the
is a Motorola
5 V square waves.
devices via a 16-bit address
8-43