Runup; Multi-Slope Ii A/D Coverter - Runup - HP 3456A Operating And Service Manual

Service
8-53. AID
Multi-Slope 11
runup, the input signal is applied to the integrator for a
set time period. This time period depends on the
operator-selected integration time ("Number of Power
Line Cycles (PLC) Integrated"). Table 8-4 lists these
PLC's and their associated integration periods.
8·54. Runup,
8-55. Figure 8-10 illustrates the in­
Runup Concept.
tegration waveform (slopes) appearing at TP402 (in­
tegrator output) of the AID Converter for a zero volt
Table 8·4. Runup Integration
HR.
Integration Mu. Digils
Time (PLC) Displayed
6 %
1 00 '
1 0 6 %
1
6 Y z
. 1 5 Y z
. 0 1 4 %
For an integration setting of 100
•
average of ten successive 1 0
input. A reference ramp (S + 4 or S - 4 slope) is switched
in for fixed times during the integration period. When
zero-crossing occurs during a slope period, the cross­
over is detected by the comparator circuit in the AID
Convener (see Figure 8-11). Zero-crossing information
from the comparator is sent to the Inguard Logic. The
I nguard Logic circuits send back to the AID Converter
the proper logic signals to reverse the direction of the
slope for the next slope period. The circuits that do the
actual slope direction change are shown in the "Logic
and Decoding Circuits" box. Switching the Y I and Y2
circuit paths from ground
changes the integrator output from a S + 4 slope
S - 4 slope. A S + 0 or S -
the end of each AID count period.
Figure 8·10. Runup Slope For Zero Volts Input 1.1 PLC).
8-10
During
Converler-Runup.
T ime
Periods.
In r n
teg atio Time Periods
Hz
In
Milliseconds
50 60 Hz
1 66.67
200
20 1 6 .67
2 1 .6 7
. 2 . 1 6 7
the digitally derived
PLC,
readings is used.
PLC
10
- 1 2 Va (reference voltage)
10
0 period (no slope) occurs at
lUC "[H"ttlef
.
..
.
",,, "
8-56. Figure 8-10 shows an initial runup (S - 4) of 4
AID counts for a . l PLC selling. For I , 10, and 100
PLC settings, the S
This causes the observed dc offset to be different when
these other PLC's are selected.
8-57. The small negative pulse preceeding the first S
slope has no circuit significance. This pulse is due to
capacitive coupling of the gate drive pulse through the
Fet switches in the AID Converter's input.
8-58. When .01 PLC is selected for zero volt input. the
waveform at TP402 resembles that of a dual-slope con­
verter. The first slope in Ihis waveform is the beginning
of Ihe rundown cycle. The small negative pulse
(preceding the first slope) lasts for the entire integration
period .
' 1 2 V �
' � '
- 1 2 h
l r
0& I
Figure 8·1 1 . Slmphfled Zero·Crosslng Circuit
lAID Converter).
8-59. Figure 8-12 illustrates the integration waveforms
(slopes) for a full-scale input ( - J O V) and a 50070 of full­
a
scale input ( - 5 V) when . 1 PLC is selected. Since the in·
tegrator circuit inverts the input signals, the negative in·
puts illustrated result in positive outputs. A mirror im­
age of the waveforms illustrated in 8-12 would result if
the input signal polarities are reversed . TI is the initial
time period (before a S + 4 slope is applied) when the cir­
cuit is integrating just the input voltage. During the T2,
T3, etc. periods, a slope voltage plus the input voltage
are applied simultaneously to the integrator's input.
After the initial 4 AID count period (T2) and after each
of the following 10 AID count periods
slope condilion occurs. This is called S ± O (T4 period,
see upper right area of Figure 8-12). Any charging dur·
ing these S ± 0 periods is the result of the input signal
voltage. The V I circuit resistor is switched to - 1 2 Va
with the Y2 path to ground for a S + 0 period. The V2
circuit resistor is switched to - 1 2 Va with the V I path
to ground for a S - 0 period. This alternate pattern com­
pensates for any V I/V2 resistance differences that could
affect the circuit's accuracy.
Model 3456A
- 4 slope lasts for 8 AID counts.
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