Autozero (Az); Input Amplifier - HP 3456A Operating And Service Manual

Service
nodes where phase cancellation will occur. The HAF
(High Analog Filter) logic signal, via comparator
UI04b, will open Fet switches QI21 and Q I I I when the
filter is enabled (see Figure 8-6). When HAF is low
(filter disabled), QI21 and Q I l I will be closed. Q 1 2 1
presents a feedback path t o prevent U 106 from going in­
to saturation and Q I I I grounds the output of the filter
so the source of Fet's Q 1 01 and Q 1 14 will be clamped to
ground.
8-38. Aulozero. Autozero (AZ), which can be disabled
or enabled with the front panel AZ button, is used to
compensate for offsets in the DC Input Amplifier. AZ is
enabled when the 3456A is first turned and also when
the front panel reset button is pressed. Two separate
measurements are taken during an input measurement
cycle with AZ enabled. The first is taken with Fet switch
QI04 closed. This shorts the Input Amplifier's input to
ground at which time its DC offset is measured and
stored in Inguard memory. The second, the input signal
measurement, is taken with QI04 open (short to Input
amplifier removed) and Fet switch QI03 closed. The DC
offset error stored in memory is subtracted from the in­
put signal measurement with the result sent to the main
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controller in the Outguard for front panel display. The
345 A will continue to toggle between Q I 04 and QI03
takmg two measurements for each input measurement
thus allowing for correction of any zero drift error in­
troduced by the DC Input Amplifier.
8-39. When AZ is disabled, one "zero offset" measure­
ment is taken and stored in memory-this single offset
value is subtracted from each of the following input
signal measurements. The 3456A reading rate is
therefore increased with AZ disabled since only one
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Figure 8·7. Simplified Schematic for Input Amplifier.
measurement is taken for each reading cycle. The zero
offset value in memory is updated when a change in the
instrument's state is made (e.g. range, function, etc.
change). In addition, Fet switching transients, which
may affect high impedance networks connected to the
3456A's input, will be eliminated when AZ is off.
8·40. Input Amplifier.
8-41. General. The Input Amplifier is a non-inverting,
selectable gain DC voltage amplifier with excellent com­
mon mode rejection (CMR) and accurate gain. The
bandwidth of the amplifier is approximately 6 kHz. To
prevent amplifier slewing, the bandwidth of the input
signal is limited to approximately 3 kHz by the Input
Switching Circuits.
8-42. Circuit Descriplion.
Simplified Schematic for Input Amplfier and Schematic
3 , Input Amplifier for the following circuit description.
The Input Amplifier
(Q310/Q3 1 I , U307, and U308) with an open loop gain
of approximately 140 dB. The Fet input stage of Q310
40.
with Q3 1 1 connected in cascade has an open loop gain
of Fets are used to provide low bias current low
noise, and high CMR. U302, a transistor package
two PNP's and two NPN's connected to sense two cur­
rent mirrors ( - 12 V Ref. to ground and - 1 8 V to
ground) provide a stable current source for these Fet's
to assure this high CMR.
8-43. U307 has an open loop gain of 10 and presents an
approximate nominal + 5 V DC level to the negative in­
put terminal of U308. The gain of U308, which is depen­
dent on the frequency, has a nominal open loop gain of
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