Runup Timing; Readout Digit Generation During Runup; Rundown - HP 3456A Operating And Service Manual

Service
1-5�1
Figure 8-15_ Slope Generation When Input Signal
Voltage and Slope Voltege are Added.
The runup timing diagram (not

8-65_ Runup Timing.

drawn to scale) in Figure 8-16 is for an integration time
of _ I PLC ( 1 .67 ms, 60 Hz; 2 ms, 50 Hz). The 130 AID
count integration period and the counts allowed for
±
each S 4 and S 0 period are fixed. This pattern will
±
remain the same for each . 1 PLC measurement cycle in­
dependent of the input voltage. When the PLC integra­
tion time is changed, the first S + 0 and S ± 4 and the
±
total AID counts change but the time allowed for each
of the remaining S 0 and S
Figure 8-17, integration time 1 PLC).
$I0Il"_
&
his
Ti_ flr .l
1 0
..
2
130
Total time for S ± 4 slopes is
Total time tOf S :l: O periods is
Figure 8·16. Runup Timing Diagrem For .1 PLC.
8-66. The initial charge on the integrator capacitor oc­
curs during the S + O period (1.2 AID counts)
preceeding the first S ± 4 slope (4 AID count period).
This time period is labeled TI in Figures 8-12 and 8-15.
8-67. The duration of the initial S + 0 and S ± 4 change
from 1 . 2 and 4 counts to 2.4 and 8 counts respectively
for I , 10, and 100 PLC settings. Figure 8-17 shows the
timing for an integration time of I PLC. Note that the
timing for . 1 and I PLC's is identical except for the in­
itial S + 0 and S ± 4, and the number of times the se­
quence is repeated. When .01 PLC is selected, a total of
only 1 3 AID counts is allocated for run up.
8 12
-
'
-
.
"
-IOY
'''''_1_''
±
4 remain the same (see
Alput'"
PLC
,
..
1 0
•
•
•
2
. . .
2
}
AID Counts
124
130
Total of
AID counts
AID
6
AID CountS
Counts
$toql.ncl
nil
62 n
... for
1 0
AID
Counts
'0 2
50
ALE·s
1300
Total time for S ± 4 slopes is
Total time tor S ± O periods ,s
Figure 8·17. Runup Timing Diagram For 1 PLC.
8-68. Each AID count is equal to 5 ALE (Address
Latch Enable) clock pulses. An ALE period is 2. 564
microseconds for 60
microseconds for 50 Hz.
8-69. Readoul Digit Generation During Runup.
counter in the Inguard microprocessor (A30-U I3) in­
crements during the positive going slope periods and
decrements during the negative going slope periods. The
counter therefore keeps an accurate accounting of the
amount of charge taken away from or added to the
original positive or negative input signal voltage. When
the integration time period is set for . 1 or greater PLC,
this counter is used to develop one or more of the most
significant digits during the runup time period. This
technique reduces the conversion time required after the
final rundown period. Table 8-5 summarizes the digit
generation for all of the integration times. A measure­
ment value of 9.87654 is used (for illustration purposes
only) to show how the measurement readout digits are
developed during runup/rundown.
Table 8·5 Reldout Digit Generation During Runup .
O.IIO� o.o,.
.... . 11.
-
101Ott'1iIo
SitoitiuOl
TIooo II'lCl
" 0.111
--
'00' " "
, "
, ,
9.87
, "
,
.
.
--
"
Fot e n in" gfl'ion Mning 01 1 0 0 PlC. thl <ligillllV de.ivO'd 1�1 •• i.
to
PlC .eading_ .. d.
I"", digits Irl de,,"loped <I"ring rundown with ,he ".0, oignificlnt
10
Ouring PLC.
digit bo-ing rounded oil.
8·70. Rundown.
8-71. As shown in Table 8-5, the Multi-Slope II run­
down technique is responsible for generating the four
least significant digits. This is done by measuring the re­
maining voltage on the integrator after runup.
Model 3456A
II�
A .... ..
I PLC
1 0
. •
. 2 •
. . .
2 }
AID Counts
1248
.
. 1 300
Total of
AID counts
A/O
52
AID CountS
Counts
Hz operation and 3.077
The
-.�
•
Do,.,
lipillcoOl
Dili1aI
-- -
-
"
654"
"0 I 66.IP
,
1.87
7654 18.87
8765
9.876 . 1 6 7
2
. 01
.""cas.i".
ge tin