Frac Circuit Description; Zero-Crossing Deleclion Circuit (U3A); Frac Enable; Rundown Timing Chart - HP 3456A Operating And Service Manual

Model 3456A
Chart. Figure 8-43 is a timing
8-206. Rundown Timing
chart that illustrates the order in which the rundown
slopes are generated and the maximum counts allowed
for each type of slope.
8-207. At the beginning of each rundown sequence,
either an 5 + 4 or 5 - 4 slope
voltage for a set time period (10 AID counts). The
selected slope reduces the integrator voltage level so that
zero-crossing is assured during the following 5 ± 4 run­
down sequence. The actual rundown counting does not
start until the following 5
these 10 AID counts are included when the rinal
measurement value is determined.
8-208. Rundown Slope Sequence.
starts with an 5 - 4 which can last for either a maximum
of 2 AID counts or a maximum of 12 AID counts,
depending on the polarity of the integrator output
voltage. When the voltage is positive at the integrator's
output at the beginning of rundown, the positive going
5 - 4 slope is going away from rather than going
towards zero. When this condition is sensed by the In­
guard Logic circuits, the 5
termination occurs within 2 AID counts after the 5 - 4
slope is started. At this time, Inguard Logic lets an 5 + 0
period pass through and then (after 5 + 0 period) sends
the command for an 5 + 4 slope. The 5 + 4 slope can last
for a period of up to 1 2 AID counts (usually lasts for
shorter period) but stops when the AID count occurs
after zero-crossing.
5 "
••
5 - ' 5 . .
T.�
- -
-
• D
' 0 2 1 2 1 2
or
' 0
�
.ioU',
60
50
-
S
- -
+ 0 1 2 AIO
!Dnd
period lime. FrilC no! COUnting during
01
- - -
Muimum of either 2
Milximum illlowed
CoonlS
SCilla
Char! to
NOTE: no! drawn
Figure 8·43. Rundown Timing Chart.
8-209. The 5 - 3 , 5 + 2, and 5 - 1 slopes can last for the
maximum AID count periods shown (16, 17, and 1 8
respectively) but stop after zero-crossing occurs. An
S + 0 period (.4 AID counts or 2 ALE counts) occurs at
the end of each of these slope periods. FRAC is enabled
during these 5 + 0 periods but is not counting.
is applied to the integrator
- 4 slope is IUrned on but
Rundown always
- 4 slope is terminated-this
5 - 3
- -
- - - - - - - - -
2
" " 6 6
"
or
60
••
90
33
' 0 '0
S + 0
periods)
counts illlowed
8·210. FRAC is disabled at the end of the last 5 + 0
period following the 5 - I
ALE counts or 6.6 AID counts) occurring after FRAC's
disablement is allocated to the pP for making calcula­
tions relating to the input signal measurements. The 10
AID count period (5 ± 4 slope) shown at the beginning
of the Rundown Timing Chart follows this 33 ALE 5
period. FRAC is enabled again at the end of Ihis 10 AID
count period.

8-211. FRAC Circuit Description.

(FRAC Circuit) for the following circuit description.
The FRAC is part of a large loop and the focal point of
the FRAC circuit is U 1 1 , a 4-bit counter. A table show­
ing the "Q" output states for U 1 1 , during FRAC's
counHo·rive routine, is shown in Figure 8-44. Only two
of these outputs, Q c and Q D , are used for FRAC cir·
cuit operations.
8-212. The Q c output goes high on the fifth ALE
CQunt. This high accomplishes the following three
things: (1) 5trobes the counter in the MP (UI3, pin 39).
(2) A high is applied (via U2a and U2b) {Q the "D" in­
put of U I 1 (pin 6) if a zero-crossing has already occur­
red (see Figure 8-44). (3) A low is applied (via Ule, U2d
and U I f) to the load input of V I I (pin 9). A low on the
load input of U9 causes V I I 's outputs (Q D , Q c.
and Q A ) to agree with the setup data on pins 6, 5, 4, and
3 when the next ALE pulse (clk input) occurs. The out­
puts will be 1 0 0 0 if a zero-crossing had occurred (sec
U 1 1 Output Table).
8-213. The Output Table for U I I shows that FRAC
starts another 5 ALE count cycle immediately, if zero­
o
crossing has not occurred (e.g. outputs change from 0 I
0 at 5th ALE count to 0 0 0 0 at count I). I f zero­
o
crossing has taken place, the outputs change from 0 I 0
at the 5th ALE count to I 0 0 0, the wait state (Q D
high, an S + O period). Counter U I I is cleared to all
zeros on the next clock pulse and starts another 5 ALE
cycle .
8-214. Zero-Crossing Deleclion Circuit (UJa).
crossing is sensed by U3a (exclusive-OR gate) when
HCP (High True, Compare) changes states. The output
of V3a goes high at this time, (high on pin 2 of NAND
gate U2a) so that the "D" input of U I 1 will go high
when the next 5th ALE count occurs.
8-215. The polarity bit line (HSA) is one of the inputs
to U3a (pin 2). The other input line is the HCP line from
the AID Converter (U3a, pin I). To follow the opera·
tion of U3a for each type of slope, refer to the 3-bit
slope code (HSA, HSB, H5C) in Figure 8-44. For exam­
ple, when the H5A polarity bit is "0", the HCP line will
go high when zero-crossing occurs. The output of U3a
goes high with these inputs.
The FRAC is enabled at the

8-216. FRAC Enable.

beginning of a rundown slope sequence by the logic low
Service
+
slope. The S 0 period (33
+
Refer to Figure 8·44
OS,
Zero·
8-39
0