Clock Generator; Address Bus Structure - HP 3456A Operating And Service Manual

Service
f TSC (pin 39)--Tri-Stote Control. This line is tied
to ground by 11 I/P I I during the run (normal) opera­
tion. When the TSC line is tied to + 5 V by P I I ,
the address lines and the Read/Write line go into the off
or high impedance state.
g.
RST( pin 40)--Reset. This input is used to start the
pP from a power-down condition (initializes pP). See
Paragraph 8-238 (A4U14 Clock Generator circuit) for a
description of how this delayed RST is generated.
....fE
8-235. The Inguard
requires only one
supply (pm 8). The Halt line (pin 2) is disabled by tieing
it to + 5 V via a pull-up resistor.
8-236. Clock Generator. The
overlapping clock inputs (411 and 412) required for the pP
operation are supplied
(A4UI4). The output frequency (f o ) of UI4 is deter­
mined by the frequency of the crystal (VI) connected to
(0
pin 2. The phase I (411) and phase 2 (1P2) outputs are 1 . 5
MHz (f o ), 0 V + 5 V square waves that appear at pins
1 5 and 1 3 respectively.
8-237. A buffered output (Bus 412, pin 7) connected to
the Master Clock line, is used for circuits on both the A3
and A4 boards. A 3 MHz output (2x f o , A4UI4 pin 5 ) is
used as an input to the circuit that generated OBE.
8-238. The reset function of UI4 (pin 12 input, pin 14
output) in conjunction with the Power Supply Ready
line generates the reset CRST-L) for the #LP. This reset
, I ' , '
i
L
..
S""
1 5
ROM Select Bit. If bit
space.
12
0
3
•
1 5 1 4 1 1 1
1 5
is not true.
8-44
all
+
5 V power
two-phase non­
by the Clock Generator
BUI
1 8
Bit
Alldrlu
.
,' ROM Add"" Fi"d
is high (true!. the address is in ROM
,
'
6
9
0
7
.
are the peripheral select bits.
Figure 8·46. Address Bus Structure.
(negative-to-positive transition) initializes the #LP at
power turn-on. A negative-to-positive transition occurs
of on the Power Supply Ready line at power-on after
(delayed Iransistion) the Outguard Power Supply
V) is up and ready for operation. The output reset line
of UI4 (pin 14) is also used at turn-on to initialize the
HP-IB Interface Adapter (A3U9).
8-239. Address Bus.
110
is illustrated in Figures 8-46a, b, c, and d. Each memory
location and device has a unique address. The pP
must output an address before any data transfer can
take place.
a. Bit 1 5 is the ROM select bit. When this bit is true
(high), the address is in ROM space. Bits 14-0 are used
for the ROM address field (32 K bit field).
b. If bit 15 is not true (Iow), then bits 14-11 are the
peripheral select bits. By encoding these 4 bits, there are
16 peripheral addresses available when the bits are
decoded. The decoded addresses are used as peripherasl
select strobes.
c. When bits 14-11 are all low (zero's), RAM space is
selected. The remaining bits (10-0) are for RAM address
locations so there is room for 2 K (2048) RAM location
(one byte per location).
d. When bits 14-1 I are 1 0 0 0 respectively, HP-IB is
selected. The HP-lB Interface Adapter (A3U9) has 8
working registers. The low bits (2, I , 0) are used for
register select.
�I
�
�
1 4 - 1 1
When Bits
0
\
�
1 4· 1 1
When Bits
HP-IB is selected.
Model 3456A
The 16-bit Address Bus structure
RAM Address LoCations
are all low, RAM is selected.
2· 0
/
.
are this pattern, Bits are us-
. ,
.d
register select
bits (HP-la Inter·
face h "
w o r k i n g
registersl.
-
( +
5
�
HP-IB
,